Electrical computers: arithmetic processing and calculating inventions 08/07

20070203962 - Methods and apparatus for providing a booth multiplier: Methods and apparatus for converting a radix 2 multiplier to respective groups of radix 4 encoded bits representing numbers of the group consisting of −2, −1, 0, 1, 2, wherein the set of encoded bits includes: a first bit that is true when the associated number is 2, a second... Agent: Kaplan Gilman Gibson & Dernier L.L.P.

20070203961 - Multiplicand shifting in a linear systolic array modular multiplier: Embodiments of apparatuses and methods for multiplicand shifting in a linear systolic array modular multiplier are disclosed. In one embodiment, an apparatus includes two processing elements of a linear systolic array. One processing element includes multiplication logic, multiplicand shift logic, an adder, modulus logic, and modulus shift logic. The multiplication... Agent: Intel Corporation C/o Intellevate, LLC

20070203963 - Portable computer: A portable computer includes a base unit, a cover unit, a main keyboard, and an input device. The cover unit is pivotably connected to the base unit. The main keyboard is mounted to the base unit. The main keyboard includes a plurality of keys. The input device is replaceably mounted... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070203964 - Multiplier and arithmetic unit: A multiplier has a multiplication array in which partial products are generated by performing multiplication between a multiplier and a multiplicand, and a partial product control circuit which generates an enable signal for activating an effective region in the multiplication array corresponding to effective figures of the multiplier and the... Agent: Young & Thompson

20070203965 - Conversion of floating-point numbers from binary into string format: A method, system, and computer program product that convert a real number from a floating point representation to a character string. Mantissa bits are extracted from the floating-point representation of a value into an integer format. The mantissa bits of the integer format may be shifted left by a number... Agent: Csa LLP

20070203966 - Transcutaneous analyte sensor: The present invention relates generally to systems and methods for measuring an analyte in a host. More particularly, the present invention relates to systems and methods for transcutaneous measurement of glucose in a host.... Agent: Knobbe Martens Olson & Bear LLP

20070203967 - Floating-point processor with reduced power requirements for selectable subprecision: A method and apparatus for performing a floating-point operation with a floating-point processor having a given precision is disclosed. A subprecision for the floating-point operation on one or more floating-point numbers is selected. The selection of the subprecision results in one or more excess bits for each of the one... Agent: Qualcomm Incorporated

20070198618 - Magnetic memory device using magnetic domain motion: Example embodiments may provide a magnetic memory device. The example embodiment magnetic memory devices may include a plurality of memory tracks, bit lines, connectors, a first input portion, and/or selectors. The memory track(s) may be stacked on a substrate to form a multi-stack. A plurality of magnetic domains may be... Agent: Harness, Dickey & Pierce, P.L.C

20070198620 - Modeling environment with generally accessible variables for dynamically linked mathematical representations: An electronic device capable of graphical data analysis is provided. The device includes a processor capable of manipulating numerical data and a graphical data. An input is provided for issuing instructions to the processor to manipulate the numerical data and graphical data. The device includes a memory device, a software... Agent: Texas Instruments Incorporated

20070198621 - Compression system and method for accelerating sparse matrix computations: The present invention involves a sparse matrix processing system and method which uses sparse matrices that are compressed to reduce memory traffic and improve performance of computations using sparse matrices.... Agent: Baker & Daniels LLP

20070198619 - Reconfigurable circuit: A reconfigurable circuit is provided, which includes a first arithmetic unit that performs addition or subtraction of a first input data and a second input data and outputs output data, and a first selector that selects an output data of the first arithmetic unit or a third input data and... Agent: Staas & Halsey LLP

20070198622 - Method for fast satd estimation: A method for determining an encoding cost for a block of video data includes providing an image frame, partitioning the image frame into multiple blocks, obtaining a difference matrix for one of the multiple blocks, performing a part of an FHT (Fast Hadamard Transform) for the difference matrix including at... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070198623 - Fast fourier transformation apparatus, ofdm communication apparatus and subcarrier assignment method for ofdm communication: Output terminal 340 extracts specific subcarrier data assigned by a base station from at least one of a plurality of butterfly operation sections provided in output terminal 340. The butterfly operation sections in first node 320, second node 330, and output terminal 340 make only butterfly operation sections relating to... Agent: Greenblum & Bernstein, P.L.C

20070198624 - Using a document model to create and maintain dynamic mathematic representations through problem spaces: A device operable to maintain a document comprising a processor, a first problem space including a first variable having a first value, and a second problem space including a second variable having a second value, the first and second variables and the first and second values stored such that when... Agent: Texas Instruments Incorporated

20070198625 - Conditional negating booth multiplier: An angle rotator performs angle rotation of an input complex signal in the complex plane according to an angle θ. The angle rotator includes a coarse stage rotation and a fine stage rotation. The two specific amounts of rotation are obtained directly from the original angle, without performing iterations as... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070198626 - Semiconductor memory device: A memory device includes an error detection and correction system with an error correcting code over GF(2n) wherein the system has an operation circuit configured to execute addition/subtraction with modulo 2n−1, and wherein the operation circuit has a first operation part for performing addition/subtraction with modulo M and a second... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070192389 - Method for generating a dynamic index: Disclosure is a method for randomly and dynamically generating a dynamic index, incorporated in a dynamic index system to improve the color performance of a display, comprises: transmitting video data to the dynamic index system; dynamically generating a substantially random number by a pseudo-random number generating unit; selecting the m... Agent: Birch Stewart Kolasch & Birch

20070192390 - Digital domain sampling rate converter: Techniques are described for sampling rate conversion in the digital domain by up-sampling and down-sampling a digital signal according to a selected intermediate sampling frequency. A prototype anti-aliasing filter that has a bandwidth with multiple factors is stored in memory. The techniques include selecting an intermediate sampling frequency to be... Agent: Qualcomm Incorporated

20070192391 - Direct digital synthesis radar timing system: A direct digital synthesizer (DDS) drives a receive sampling gate at a frequency that is offset from a transmit pulse frequency to produce an expanded time sampled echo signal. The frequency offset generates a smoothly slipping phase between realtime received echoes and the sampling gate that stroboscopically expands the apparent... Agent: Thomas Edward Mcewan

20070192392 - Decimation filter: A system and method for decimating a digital signal is disclosed. The system includes an input to receive digital data, a control input to receive a desired decimation rate, and an integrator stage responsive to the input. The system also includes a variable rate down sampling module responsive to the... Agent: Larson Newman Abel Polansky & White, LLP

20070192393 - Method and system for hardware and software shareable dct/idct control interface: Certain aspects of a method and system for hardware and software shareable DCT/IDCT control interface are provided. A single DCT/IDCT interface may be utilized to provide hardware or software control of a DCT/IDCT module. During hardware control the DCT/IDCT module may be utilized for JPEG compression, for example. During software... Agent: Mcandrews Held & Malloy, Ltd

20070192394 - Processor and method for performing a fast fourier transform and/or an inverse fast fourier transform of a complex input signal: A processor for performing a Fast Fourier Transform and/or an Inverse Fast Fourier Transform of a complex input signal comprises a first stage for passing the input signal to a second stage when a Fast Fourier Transform procedure is to be performed and for swapping the real and imaginary components... Agent: Venable LLP

20070192395 - Method for database-driven estimate of an output quantity in a k-dimensional value range: Method for the database-driven estimate of an output quantity in a k-dimensional value range. The method includes determining a location probability range Ri for a k-dimensional output quantity for an element i of a measurement series {i=1, . . . ,n}, in which the location probability range Ri is limited... Agent: Greenblum & Bernstein, P.L.C

20070192396 - Packed add-subtract operation in a microprocessor: A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated source registers of a register file and the sum and difference results of such operation are packed into respective top and bottom half-word... Agent: Schneck & Schneck

20070192397 - Cryptosystem based on a jacobian of a curve: A cryptosystem has a secret based on an order of a group of points on a Jacobian of a curve. In certain embodiments, the cryptosystem is used to generate a product identifier corresponding to a particular product. The product identifier is generated by initially receiving a value associated with a... Agent: Lee & Hayes PLLC

20070192398 - Booth multiplier with enhanced reduction tree circuitry: Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e.g., CDMA) system. A modified Booth multiplication system and process determine a multiplicand, A, and a multiplier, B. Radix-m, (e.g., radix-4) Booth recoding on B generates “n” multiplication factors, where “n,” an integer,... Agent: Qualcomm Incorporated

20070192399 - Power-efficient sign extension for booth multiplication methods and systems: Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e.g., CDMA) system. Power-efficient sign extension for Booth multiplication processes involves applying a sign bit in a Booth multiplication tree. The sign bit allows the Booth multiplication process to perform a sign extension... Agent: Qualcomm Incorporated

20070185944 - Handheld electronic device having reduced keyboard and multiple password access, and associated methods: A reduced keyboard handheld electronic device and associated method that utilizes a plurality of passwords for controlling access thereto. The handheld electronic device has a non-predictive keystroke interpretation system, such as a multi-tap system. At least one of the passwords is valid and accepted when input using a keyboard of... Agent: Eckert Seamans Cherin & Mellott

20070185946 - Method and apparatus for matching portions of input images: A method and apparatus for finding correspondence between portions of two images that first subjects the two images to segmentation by weighted aggregation (10), then constructs directed acylic graphs (16,18) from the output of the segmentation by weighted aggregation to obtain hierarchical graphs of aggregates (20,22), and finally applies a... Agent: Fleit Kain Gibbons Gutman Bongini & Bianco

20070185945 - Reilible recording of input values: The invention relates to a system and a method for the securely recording input values used for processing in a safety-oriented processor. In order to allow input values to be recorded securely by means of a non-safety-oriented operating device, a first value which is input via input means is displayed... Agent: Siemens Corporation Intellectual Property Department

20070185947 - Frequency synthesizer: A frequency synthesizer includes: a signal generation section for outputting a signal having a desired frequency; a noise generation section for generating a noise to be a set value; and a noise adding section for adding the noise from the noise generation section to the signal from the signal generation... Agent: Sughrue-265550

20070185948 - Method for modular multiplication: In a method for modular multiplication using a multiplication look-ahead process for computing a multiplication shift value and a reduction look-ahead process for computing a reduction shift value, a modulus is first transformed into a transformed modulus that is greater than said modulus. The transformation is carried out such that... Agent: Lerner Greenberg Stemer LLP

20070185949 - Demodulation of a multi-level quadrature amplitude modulation signal:

20070185950 - Modular multiplication processing apparatus: A modular multiplication processing apparatus is provided that can process modular multiplication of data exceeding a bit length which a coprocessor can process, by using the coprocessor based upon Montgomery multiplication. In the apparatus, data to be subjected to modular multiplication is decomposed, and the decomposed data elements are respectively... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070185951 - Specialized processing block for programmable logic device: A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for rounding the result. The rounding circuitry can selectably perform round-to-nearest and round-to-nearest-even operations. In addition, the bit position at which rounding occurs is preferably selectable. The specialized processing... Agent: Fish & NeaveIPGroup Ropes & Gray LLP

20070185952 - Specialized processing block for programmable logic device: A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block... Agent: Fish & NeaveIPGroup Ropes & Gray LLP

20070185953 - Dual mode floating point multiply accumulate unit: Included are embodiments of a Multiply-Accumulate Unit to process multiple format floating point operands. For short format operands, embodiments of the Multiply Accumulate Unit are configured to process data with twice the throughput as long and mixed format data. At least one embodiment can include a short exponent calculation component... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070180003 - Exclusive set system constructions including, but not limited to, applications to broadcast encryption and certificate revocation: An (n,k,r,t)-exclusive set system over a set U includes elements Sƒ each of corresponds to a polynomial ƒ(u) in one or more coordinates of uεU. The polynomial is zero on U\Sƒ but is not zero on Sƒ. In some embodiments, an asymptotically low key complexity k is provided.... Agent: Macpherson Kwok Chen & Heid LLP

20070180006 - Parallel operational processing device: In a parallel operational processing device having an operational processing unit arranged between memory blocks each having a plurality of memory cells arranged in rows and columns, the respective columns of each memory block are alternately connected to the operational processing units on the opposite sides of the memory block.... Agent: Buchanan, Ingersoll & Rooney PC

20070180004 - Apparatus and method for precision binary numbers and numerical operations: An method and/or apparatus for representing and/or operating on numerical values in binary systems whereby numerical values having integer and fractional portions are stored in non-contiguous memory locations.... Agent: Quine Intellectual Property Law Group, P.C.

20070180005 - Signal processing system and method of managing terminal number in signal processing system: A signal processing system manages terminal numbers as a whole system without being affected by exchange of substrates and performs signal processing of intended object. A control unit sequentially assigns terminal numbers to substrates in numerical order of slots of each kind and validates only terminal numbers regarding the slot... Agent: Frommer Lawrence & Haug LLP

20070180007 - Barrel shift device: When a barrel shift device is divided into pipeline registers and a shift process is executed in a multistage process stage, by decoding a second control signal for controlling a shift amount of a second shift circuit 50 using a decoding circuit 20, it is detected at what digit positions... Agent: Mcdermott Will & Emery LLP

20070180008 - Register-based shifts for a unidirectional rotator: A processor having a unidirectional rotator configured to shift or rotate data in one direction is disclosed. The processor also includes a control unit having logic configured to modify a shift value specified by a registered-based shift, or rotate, instruction in an opposite direction, the modified shift value being usable... Agent: Qualcomm Incorporated

20070180009 - Rfid tag with random number generator having a noise-based input: A random number generator for an RFID tag is described. In one such embodiment the random number generator includes a noise-controlled component comprising a noise source circuit that outputs a noise-based signal operable to generate random numbers from the noise-based signal. The noise-based signal is variable due to noise.... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070180011 - Fast fourier transform processor: An implement method of a FFT processor comprises the following steps. First, a 21 point FFT processor, which has an output and an input receiving a 2n+1 point data, is provided. A 2n-point FFT processor having an input and an output is provided. Sequentially, a multiplexer, which has a first... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070180010 - System and method for iteratively eliminating common subexpressions in an arithmetic system: A method for reducing operations in a processing environment is provided that includes generating one or more binary representations. One or more of the binary representations are included in one or more linear equations that include one or more operations. The method also includes converting one or more of the... Agent: Baker Botts L.L.P.

20070180012 - Approximating function properties with expander graphs: Function properties may be approximated using an expander graph. For example, an approximate average of a function may be determined by randomly exploring an expander graph. Values of the function are associated with vertices of the expander graph. The expander graph is randomly explored by traversing edges and encountering vertices.... Agent: Lee & Hayes PLLC

20070180013 - Method and apparatus for user function variable processing system and prompt: A user inputs information, such as a mathematical function, composed of variable strings, functions, characters, expressions, etc., into an information input field connected to a function variable processing system. In one embodiment, the function variable processing system breaks down the information into tokens. The tokens are then processed to detect... Agent: Townsend And Townsend And Crew LLP

20070180014 - Sparce-redundant fixed point arithmetic modules: A fixed-point arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive bits comprising a sparse-redundant representation of the integer. A converter converts 1-redundant representations of the integer... Agent: Lsi Logic Corporation

20070180015 - High speed low power fixed-point multiplier and method thereof: Provided are a high speed and low power fixed-point multiplier and method thereof. The multiplier includes: a partial product calculation unit for dividing input data into a plurality of bit groups, each bit group having a predetermined number of bits, generating partial products by independently multiplying a fixed coefficient for... Agent: Ladas & Parry LLP

20070180016 - Method of operand width reduction to enable usage of narrower saturation adder: An electronic computing circuit for implementing a method for reducing the bit width of two operands from a bit length N to a reduced bit length M, thus, M<N. To enable a wider re-usage of existing designs or building blocks being all specialised to the usual bit length of a... Agent: International Business Machines Corporation