Electrical computers: arithmetic processing and calculating inventions 07/07

20070174373 - Vehicle control apparatus having event management unit: In a vehicle control apparatus having an arithmetic processing unit including an arithmetic unit, a storage unit and a communication unit, and an input/output unit including an signal input unit or a signal output unit and a communication unit, the arithmetic processing unit is connected to the input/output unit via... Agent: Crowell & Moring LLP Intellectual Property Group

20070174371 - Hardware-efficient phase-to-amplitude mapping design for direct digital frequency synthesizers: A hardware-efficient mapping circuit uses a controller to down select signed shift values from the control signal (MSBs) for a particular phase angle. Shifter blocks shift the data signal (LSBs) by the respective shift values. The shifted data signals are added/subtracted from a base value decoded from the control signal... Agent: Koppel, Patrick & Heybl

20070174372 - Programmable processing unit having multiple scopes: In general, in one aspect, the disclosure describes a processing unit that includes a memory, an arithmetic logic unit, and control logic having access to program instructions of a control store. The control logic includes logic to access multiple sets of variables, variables in the different sets of variables being... Agent: Blakely Sokoloff Taylor & Zafman

20070174374 - Pseudorandom number generator and pseudorandom number generation program: A pseudorandom number generator (1) has a first linear feedback shift register (2), a second linear feedback shift register (3), an initial value generator (4), a polynomial coefficient generator (5), and a pseudorandom number output unit (6). The initial value generator (4) generates initial values and supplies the same to... Agent: Nath & Associates

20070174376 - Digital filter design system and method: A new method of designing digital filters for specific magnitude and phase requirements that minimises the filter's group-delay given arbitrary error tolerances is presented in this patent application. The method is extended to include optimising the original filter design based on the group-delay minimisation routine. A particular example that describes... Agent: St. Onge Steward Johnston & Reens, LLC

20070174375 - Method and system for selecting effective tap values for a digital filter: Systems and methods are provided for determining effective tap values for a digital filter. A first plurality of vectors is generated, wherein each of the first plurality of vectors represents a set of tap values for the filter at a first resolution. A best vector is selected from the first... Agent: Texas Instruments Incorporated

20070174377 - A chaos theoretical exponent value calculation system: The present invention provides a system for analyzing a time series signal by a method of Chaos Theory and calculating a chaos theoretical exponent value. It is a chaos theoretical exponent value calculation system comprising: a means for receiving an input of predetermined parameters, a means for reading a time... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070174378 - Computation of logarithmic and exponential functions: Efficiency of computation of logarithmic and exponential functions may be improved using multiplication by pre-computed coefficients to obtain intermediate products.... Agent: Venable LLP

20070174379 - Pre-saturating fixed-point multiplier: A pre-saturating multiplier inspects the operands to a multiply operation prior to performing any multiplication. If the operands will cause an overflow requiring saturation, the multiplier outputs the saturated value without multiplying the original operands. In one embodiment, parameters derived from the operands are altered such that when the multiply... Agent: Qualcomm Incorporated

20070168406 - Complementary linear feedback shift registers for generating advance timing masks: A mask required to generate a time-offset version of a PN code may be generated by constructing a Galois linear feedback shift register (LFSR) that is complementary to a Fibonacci LFSR that generates the PN code, clocking the Galois LFSR a number of times equal to the time offset, and... Agent: Tensorcomm, Inc.

20070168407 - Snr estimation using filters: The present invention provides a method of accurately determining the signal to noise ratio (SNR) using filters. Three embodiments of the invention are disclosed: the use of fixed filters, multiple filters and dynamic filters. The total noise energy is calculated by applying low pass and high pass filters. The minimum... Agent: Ashok Tankha, Lipton, Weinberger & Husick

20070168408 - Parallel system and method for acceleration of multiple channel lms based algorithms: A parallel system for performing LMS coefficient adaptation includes a data memory, a tap memory, and two or more LMS hardware units. The LMS hardware units utilize data stored in the data memory and coefficients stored in the tap memory for performing multiple LMS coefficient adaptations in parallel.... Agent: Norman H. Zivin Cooper & Dunham LLP

20070168409 - Method and apparatus for automatic detection and identification of broadcast audio and video signals: This invention relates to the automatic detection and identification of broadcast programming, for example music, speech or video that is broadcast over radio, television, the Internet or other media. “Broadcast” means any readily available source of content, whether now known or hereafter devised, including streaming, peer to peer delivery or... Agent: Ted Sabety, C/o Berry & Associates, P.C.

20070168410 - Transforms with common factors: Techniques for efficiently performing transforms on data are described. In one design, an apparatus performs multiplication of a first group of at least one data value with a first group of at least one rational dyadic constant that approximates a first group of at least one irrational constant scaled by... Agent: Qualcomm Incorporated

20070168411 - Reduction calculations: An Elliptic Curve Cryptography reduction technique utilises a prime number having a first section of Most Significant Word “1” states, with N=nm−1+N1B+n0.... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070162529 - Dynamically reconfigurable processor and processor control program for controlling the same: A dynamically reconfigurable processor having a wiring structure which enables flexible mapping of a program to the processor with a small wiring area is provided. The dynamically reconfigurable processor comprises: a first arithmetic circuit group composed of arithmetic circuits of a type Ai (i=1, 2, . . . , N);... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070162530 - Modular reduction for a cryptographic process and corprocessor for carrying out said reduction: The invention relates to a cryptographic method wherein, in order to carry out a fully polynomial division of type Q(x)[U(x)/N(x)], wherein Q(x), N(x) and U(x) are polynomials, respectively a result, dividend and a divider, multiplication of the two polynomials is carried out followed by displacement of the bits of the... Agent: Buchanan, Ingersoll & Rooney PC

20070162531 - Flow transform for integrated circuit design and simulation having combined data flow, control flow, and memory flow views: The exemplary embodiments of the invention provide a method, system and software for developing and simulating an integrated circuit architecture. An exemplary method includes inputting an algorithm using an instruction language having control information; decomposing the algorithm to a plurality of tasks; for each task of the plurality of tasks,... Agent: Gamburd Law Group LLC

20070162532 - Method for generating at least one random number: In a method for generating at least one random number for a system, at least one pseudo-random input value is used which is generated while taking into consideration of a boundary condition.... Agent: Kenyon & Kenyon LLP

20070162533 - Circuit for fast fourier transform operation: A circuit for a fast Fourier transform (FFT) operation is provided. The FFT operation circuit includes a plurality of butterfly operation units connected in series. Each of the plurality of butterfly operation units reads a signal in the order in which the plurality of butterfly operation units perform complex multiplication,... Agent: Sughrue Mion, PLLC

20070162534 - Protection of a calculation performed by an integrated circuit: A method and a circuit for protecting a digital quantity over a first number of bits, in an algorithm executing at least one modular exponentiation of data by the quantity, the steps including at least one squaring up and at least one multiplication and implementing, for each bit of the... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070162535 - Rounding floating point division results: A method for determining the correct result and the correct guard and sticky bits to obtain a more accurate result in floating point divide operations is presented. An intermediate divide result or quotient is obtained from a multiply-add hardware pipeline of a floating point processor. Remainders are calculated using the... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070156795 - Data-generation supporting system, data-generation supporting apparatus, and computer program product: A data-generation supporting system includes an template generating unit that generates a document type template from metadata for inputting a combination, the metadata defining a class and properties indicating attributes of an instance belonging to the class; a combination-information generating unit that receives a combination of constituent elements of the... Agent: Charles N.j. Ruggiero Ohlandt, Greeley, Ruggiero & Perle, L..l.p.

20070156796 - Method and device for calculating a function from a large number of inputs: In an input process, a circuit and an input bit to the circuit are inputted to a plurality of computers. Firstly, one computer performs calculation and transmits the calculation result to another computer of the computers. Next, the another computer which has received the calculation result performs the next calculation.... Agent: Scully Scott Murphy & Presser, PC

20070156797 - Protection of a calculation performed by an integrated circuit: The calculation, by an electronic circuit, of a result of an integral number of applications of an internal composition law on elements of an abelian group, by successive iterations of different steps according to the even or odd character of a current coefficient of a polynomial representation of said integer,... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070156798 - Random number derivation method and random number generator using same: Disclosed is a method for deriving random numbers at a higher speed than ever before while maintaining desired randomness without spoiling uniformity of the occurrence frequency of each random number. One pulse included in one of two or more mutually-independent random pulse sequences and one pulse included in one of... Agent: Stephen M. De Klerk Blakely, Sokoloff, Taylor & Zafman LLP

20070156799 - Multi-stage finite impulse response filter processing: In one aspect, the invention is a method of emulating an n-stage finite impulse response (FIR) filter. The method includes connecting an output of a one-stage FIR filter to an input of the one-stage FIR filter to form a feedback path. The method also includes configuring the one-stage FIR filter... Agent: Valeo Raytheon Systems, Inc. C/o Daly, Crowley, Mofford And Durkee, LLP

20070156800 - Multi-standard multi-rate filter: A method is provided for decimating a digital signal by a factor of M and matching it to a desired channel bandwidth. The method applies the digital signal input samples to a (M−1) stage tapped delay line, downsamples the input samples and the output samples of each tapped delay line... Agent: Macpherson Kwok Chen & Heid LLP

20070156801 - Flowgraph representation of discrete wavelet transforms and wavelet packets for their efficient parallel implementation: The disclosed embodiments relate to a microprocessor structure for performing a discrete wavelet transform operation. It uses a flowgraph representation of discrete wavelet transforms (DWTs) and wavelet packets. This representation is useful for developing efficient parallel algorithms and VLSI architectures. As examples, two DWT architectures for Haar wavelets and three... Agent: Perman & Green

20070156802 - Method and apparatus for initializing interval computations through subdomain sampling: One embodiment of the present invention provides a system that uses a computer to evaluate a function within a domain using an interval computing technique. During operation, the system receives the function and the domain over which the function is to be evaluated. Next, the system creates a set of... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20070156803 - Overflow detection and clamping with parallel operand processing for fixed-point multipliers: A method and apparatus for overflow detection and clamping with parallel operand processing for fixed-point multipliers is disclosed. The invention predicts when a multiplication of a number of operands will exceed a pre-determined number of bits based upon the fixed-point format of the operands. The prediction is performed in parallel... Agent: Whyte Hirschboeck Dudek S.c.