Electrical computers: arithmetic processing and calculating inventions 05/07

20070124351 - Web service system, schedule execution apparatus and control method thereof: A schedule execution unit accesses a storage unit for storing a call list registered in a database and determines whether or not there is a Web service call to be executed. If the presence of a Web service call to be executed is confirmed, the schedule execution unit reads out... Agent: Canon U.s.a. Inc. Intellectual Property Division

20070124352 - Efficiency implementation of the cordic algorithm fro complex phase rotation: An improved implementation of the CORDIC algorithm that considers the n highest-order active bits in each stage of the CORDIC implementation resulting in increases in the precision of the final result by 2n. The rotational angle increment n−1 possible magnitudes that can be either positive or negative. The rotational angle... Agent: Philips Intellectual Property & Standards

20070124354 - Method for composing lookup table and searching index thereof: A method for composing a lookup table and searching indexes thereof is provided. The method includes the steps of: a) composing a lookup table using a symmetry of a sine and a cosine function; b) changing and setting a gain of a DCO by reflecting a lookup table size in... Agent: Blakely Sokoloff Taylor & Zafman

20070124353 - System and method for generating a probability distribution of computer performance ratios: A system and method for generating a probability distribution indicating the probability of a range of performance ratios between computer systems. Benchmark and/or other testing results are obtained for both computer systems. For each test, a ratio of one system's performance to the other is calculated. The ratios and/or testing... Agent: Sun Microsystems, Inc. C/o Park Vaughan & Fleming, LLP

20070124355 - Support of deep power savings mode and partial good in a thermal management system: A computer implemented method, data processing system, and processor are provided for managing a thermal management system. A determination is made as to whether a plurality of digital thermal sensors is faulty or functional. A power savings mode of at least one unit within the integrated circuit associated with the... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070124356 - Correlation method to adaptively operate in time varying phase and correlator thereof: Disclosed is a correlation method to adaptively operate in a time varying phase and a correlator thereof. A correlation method according to the present invention includes performing the first correlation according to a certain reference value and a certain reference interval for correlation of a received signal; calculating an average... Agent: Sughrue Mion, PLLC

20070124357 - Methods and apparatus fro performing calculations using reduced-width data: Methods, apparatus, and articles of manufacture for performing calculations using reduced-width data are disclosed. In particular, an example method determines reduced-width data values associated with generating and evaluating functions. Some of the reduced-width data values are stored within instructions in an instruction memory during a compile phase and retrieved from... Agent: Brinks Hofer Gilson & Lione/marvell

20070118580 - Apparatus and method to find the maximum or minimum of a set of numbers: An apparatus for determining a best number, representing a maximum or minimum of a set of numbers, includes a first comparator 3 having a latency of at least one clock cycle to compare a current number with a current best score and to output a corresponding first comparator signal 7... Agent: Seyfarth Shaw LLP

20070118581 - Microprocessor with random number generator and instruction for storing random data: A microprocessor includes a storage element that accumulates a variable number of bytes of random data. The microprocessor also includes a counter that maintains a count of the variable number of bytes accumulated in the storage element. The microprocessor also includes an instruction translator that translates an instruction specifying an... Agent: Huffman Law Group, P.C.

20070118582 - Microprocessor with random number generator and instruction for storing random data: A microprocessor includes a random number generator circuit (RNG) within its instruction set architecture (ISA). An RNG buffer accumulates zero or more bytes of random data generated by the RNG. An RNG counter maintains a count of the accumulated random data bytes. An instruction translator translates instructions of the ISA.... Agent: Huffman Law Group, P.C.

20070118583 - Complex coefficient transversal filter and radio communication system employing the same: A radio communication system, method, and apparatus using a complex coefficient transversal filter which removes an image are provided. Accordingly, it is possible to improve an image suppression ratio over a wide band by applying the complex coefficient transversal filter which removes an image by using a phase delay of... Agent: Sughrue Mion, PLLC

20070118584 - Apparatus and method for calculation of divisions and square roots: Non-restoring radix-2 division and square rooting procedures are provided. The proposed procedures utilize a quotient/root digit set {−1, 0, +1} and a quotient/root prediction table (QRT/RPT). The i'th quotient/root digit is determined with reference to a partial remainder from (i−2)'th iterative operation and by the quotient/root prediction table. The present... Agent: Mills & Onello LLP

20070112901 - Configurable digital filter: In one embodiment, a configurable device is provided for multiplying a plurality of digital words with a corresponding plurality of coefficients. The configurable digital filter includes: a plurality of lookup tables, each lookup table corresponding to at least one of the coefficients and operable to receive at least a portion... Agent: Macpherson Kwok Chen & Heid LLP

20070112902 - Reciprocal estimate computation methods and apparatus: In a first aspect, a first method of reciprocal estimate computation using floating point pipeline logic is provided. The first method includes the steps of (1) receiving an input value having an exponent and a mantissa when represented as a floating point number on which a reciprocal estimate computation is... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070112903 - [square root algorithm]: The present invention discloses a square root algorithm that uses a multiplication operation, an exclusive-or operation, a bit right shift operation, a bit left shift operation and a comparison operation to compute a square root for an integer in a binary form, such that more computations can be processed in... Agent: Jianq Chyun Intellectual Property Office

20070112904 - Multiplier device: Multiplier device comprising first to nth multipliers M1 to Mn for multiplying a carrier modulated information signal with first to nth mutually phase shifted and identical, substantially square wave mixing signals MS1 to MSn with 50% duty cycle. In order to eliminate fifth or higher order interferences from the output... Agent: Robert M. Mcdermott, Esq.

20070112905 - Process control with unreliable communications: Disclosed are methods and devices for controlling a process with a control signal. Iterations of a control routine are implemented to generate the control signal, and when an indication of a response to the control signal is unavailable, a feedback contribution to the control signal is maintained over one or... Agent: Marshall, Gerstein & Borun LLP (fisher)

20070106717 - Radio frequency planning with consideration of inter-building effects: A method includes providing a first set of location data using a first coordinate system that corresponds to a first building and a second set of location data using a second coordinate system that corresponds to a second building. A third set of location data is generated from the first... Agent: Siemens Corporation Intellectual Property Department

20070106718 - Fast fourier transform on a single-instruction-stream, multiple-data-stream processor: A method of performing a fast Fourier transform (FFT) in a single-instruction-stream, multiple-data-stream (SIMD) processor includes providing n-bits of input data, and implementing j number of stages of operations. The n-bits of input data are grouped into groups of x-bits to form i number of vectors so that i=n/x. The... Agent: Freescale Semiconductor, Inc. Law Department

20070106719 - Integer square root algorithm for use in digital image processing: An integer square root calculation technique determines the precise root of an input value to determine the distance between data points such as pixels in a digital image. The technique avoids division and floating point multiplication steps. An initial root estimate may be used as a seed value beginning an... Agent: Lexmark International, Inc. Intellectual Property Law Department

20070106720 - Reconfigurable signal processor architecture using multiple complex multiply-accumulate units: A reconfigurable digital signal processor (DSP) comprises: a reconfigurable data path comprising a plurality of reconfigurable multiply-accumulate (MAC) units; and a programmable finite state machine for controlling the plurality of reconfigurable MAC units. The programmable finite state machine executes a first plurality of context-related instructions that cause selected ones of... Agent: Docket Clerk

20070100920 - Hardware transformation engine: A method and apparatus for converting documents from one format to another in a speed efficient way involves a hardware module which implements several operating pipeline stages which work in parallel. The transformations are supplied and decomposed into sequences of control units. The transformation of documents consists of applying control... Agent: Marks & Clerk

20070100921 - Random number generator using jitter sampled rf carrier: A random number generator generates a string of random bits from a received RF signal source. A sample-and-hold circuit is coupled to the received RF signal source. The RF signal is sampled by a jittered clock signal from a source coupled to the sample-and-hold circuit. The frequency of the jittered... Agent: Texas Instruments Incorporated

20070100922 - Apparatus and method for signal detection in a cognitive radio-based wireless communication system: An apparatus and method for signal detection in a CR-based wireless communication system are provided. In the signal detection apparatus, a cyclic power calculator calculates the power spectral density of a cyclo-stationary and periodical signal to be detected with respect to a cyclic frequency and calculates optimum statistics using the... Agent: Dilworth & Barrese, LLP

20070100923 - Arithmethic logic and shifting device for use in a processor: An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory... Agent: Qualcomm Incorporated

20070100924 - Asynchronous signed multiplier and algorithm thereof: An asynchronous signed multiplier including N pieces of partial product generators (PPGs), an operation module and a leading-zero-bit-detector is provided. The partial product generator generates a plurality of partial product values in response to a multiplier and a multiplicand. The operation module conducts a sum-up operation on the outputs from... Agent: J.c. Patents, Inc.

20070100926 - Device and method for calculating a multiplication addition operation and for calculating a result of a modular multiplication: For calculating a result of a modular multiplication with long operands, at least the multiplicand is divided into at least three shorter portions. Using the three shorter portions of the multiplicand, the multiplier and the modulus, a modular multiplication is performed within a cryptographic calculation, wherein the portions of the... Agent: Dickstein Shapiro LLP

20070100925 - Device and method for calculating a result of a sum with a calculating unit with limited word length: For calculating the result of a sum of a first operand and a second operand, a modified second operand is calculated, which is negative and less than the modulus. Based on this modified second operand, a sum is calculated which is less than a maximally processable number of a calculating... Agent: Dickstein Shapiro LLP

20070100927 - Wide tunable polyphase filter with variable resistor and variable capacitor: Disclosed is a wideband polyphase filter using variable resistors and variable capacitors for correcting a phase and a frequency to be suitable for wideband communication. There is provided a wideband polyphase filter including: a variable resistor in which resistance varies; and a variable capacitor in which capacitance varies, wherein the... Agent: Sughrue Mion, PLLC