Electrical computers: arithmetic processing and calculating inventions 04/07

20070094317 - Method and system for b-spline interpolation of a one-dimensional signal using a fractional interpolation ratio: The present invention provides systems, methods, and computer program products for performing fractional B-spline interpolation. The fractional B-spline interpolation system includes an upsampling module and a fractional B-spline interpolation filter. The B-spline interpolation filter calculates a set of B-spline interpolation coefficients at a plurality of fine index points using the... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070094318 - Method and system for hardware efficient systematic approximation of square functions for communication systems: Certain aspects of a method and system for implementing approximation of a square function may comprise generating an output value by subtracting an absolute value of a first received input and a second received input. The generated output may be left shifted so as to generate a left shifted value.... Agent: Mcandrews Held & Malloy, Ltd

20070094319 - Digital filter and listening device: The invention concerns a digital filter. The filter comprises at least a first and a second 5 delayed summation line, whereby one of the delay lines comprise a warped filter FIR filter and the other line is a FIR filter, whereby: at least two delayed summation lines are present, midpoint... Agent: Birch Stewart Kolasch & Birch

20070094320 - Parallel adder-based dct / idct design using cyclic convolution: A device and method are described that apply 1-D and 2-D discrete cosine transforms (DCT) and inverse discrete cosine transforms (IDCT) to sets of input data, typically 8×8 or 16×16 matricies of coefficients. One device includes input lines, logic to pre-add input values and generate operands and one or more... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070088772 - Fast rotator with embedded masking and method therefor: An operand rotator (100) and method of rotating an operand is disclosed. The operand rotator (100) includes a first decoder (102) with a first input to receive an operand size indicating one of a plurality of operand sizes, a second input for receiving a rotate amount signal and a control... Agent: Larson Newman Abel Polansky & White, LLP

20070088773 - Digital signal processing apparatus: A digital signal processing apparatus comprises a main memory, a processing unit, a cache, and a rotate buffer unit. The main memory includes at least R memory banks for storing a plurality of data of digital signal. The cache is coupled between the main memory and the processing unit. The... Agent: J C Patents, Inc.

20070088774 - Computer technical solution of mixed q-nary and carry line digital engineering method: The present invention relates to the field of digital engineering method and processor, and puts forward a new digital engineering method, which could increase the operation speed. The mixed Q-nary carry line digital engineering method of the present invention includes: adding a numeral sign to each bit of numeral of... Agent: Beyer Weaver LLP

20070083576 - Arithmetic logic device having auxiliary computing unit: An arithmetic and logic device as an integral part of a processing unit is provided to achieve code size and overhead reduction. The arithmetic and logic device contains several auxiliary computing units, each of which is capable of simple arithmetic and logical operation, under the control of a control unit.... Agent: Lin & Associates Intellectual Property

20070083577 - System and method for detecting defects in a light-management film: A system and a method for detecting defects in a light-management film are provided. The system includes a first light source configured to emit light onto a first side of the film in a first predetermined region of the film. The system further includes a second light source configured to... Agent: Cantor Colburn, LLP

20070083578 - Video encoding method enabling highly efficient partial decoding of h.264 and other transform coded information: Methods and apparatus to process multimedia data enabling efficient partial decoding of transform coded data are described. A decoder device receives transform coefficients, where the transform coefficients are associated with multimedia data. The decoder device determines a set of multimedia samples to be reconstructed. In one aspect, the set of... Agent: Qualcomm Incorporated

20070083579 - Reconfigurable address generation circuit for image processing, and reconfigurable lsi comprising the same: A reconfigurable address generation circuit for image processing is configured to an arbitrary state based on configuration data generates a read address for reading out image data of pixel units having a plurality of rows and columns from a memory which stores image data. As the configuration data, there are... Agent: Arent Fox PLLC

20070083580 - Bounded signal mixer and method of operation: A method and apparatus are provided for mixing a plurality of signals within a predetermined dynamic range without clipping. In the method and apparatus, first and second signal samples are added together to obtain a first intermediate result. Then the first signal sample is multiplied with the second signal sample... Agent: Freescale Semiconductor, Inc. Law Department

20070083581 - Multiplierless fir digital filter and method of designing the same: Provided are a multiplierless FIR digital filter and a method of designing the same, in which a filtering operation is performed by not multipliers needed as many as the number of tap depending on design requirement but a small addition/subtraction circuit using extracted information after analyzing the property of a... Agent: Ladas & Parry LLP

20070083582 - Address generation method for combining multiple selection results: A method in an integrated circuit for generating an address value having a contiguous address range from a first selection result and a second selection result each being an one-of-k selection result includes selecting multiple multiplication factors being power-of-two multiplication factors and the sum of the multiplication factors being equal... Agent: Patent Law Group LLP

20070083584 - Integrated multiply and divide circuit: The principles of the present invention relate to a multiply and divide circuit configured to interactively multiply and/or divide. The circuit may handle signed and unsigned values. The circuit comprises an instruction register configured to store a multiply or divide instruction, at one input register configured to store the multiply... Agent: Workman Nydegger (f/k/a Workman Nydegger & Seeley)

20070083583 - Method for calculating a result of a division with a floating point unit with fused multiply-add: The invention proposes a Floating Point Unit with fused multiply-add, with one addend Method for calculating a result of a division with an A-register and a B-register for two multiplicand operands and a C-register for an addend operand, wherein a divide processor using a subtractive method for calculation with a... Agent: International Business Machines Corporation

20070083585 - Karatsuba based multiplier and method: A method of multiplying large integers is disclosed. Two large numbers, x and y, are provided. values are determined in accordance with the Karatsuba multiplication process based on x and y. A first and second value according to the Karatsuba multiplication method are also determined. The third value for use... Agent: Freedman & Associates

20070083586 - System and method for optimized reciprocal operations: A method and apparatus for calculating a reciprocal of an integer using a modified Newton Raphson method using one's complements instead of two's complements. The method includes determining a required precision; determining a number of iterations T responsive to the required precision; normalizing N into d; obtaining initial approximation of... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070083587 - Apparatus and method for calculating square root: An apparatus and method for calculating a square root are provided. The square root calculation apparatus calculates an approximated square root for an input value. An integer detector detects a position of a non-zero most significant bit (MSB) from the input value, and outputs an arbitrary integer value. A first... Agent: Roylance, Abrams, Berdo & Goodman, L.L.P.

20070078917 - Removable media player for mobile phones: A digital media device for providing digital media services to a mobile phone is disclosed. In exemplary embodiments, the device includes: a phone memory card that is reversibly deployable to a port of the mobile phone; and a digital media-player application residing on the phone memory card, wherein the combination... Agent: Dr. Mark Friedman Ltd. C/o Bill Polkinghorn

20070078918 - Contact shape computing apparatus and method, and computer program therefor: A contact shape computing apparatus for detecting contact between a plurality of three-dimensional solid models and computing a contact shape between two solid bodies in contact with each other includes the following elements: a collision detector operable to detect a collision or contact between the two solid bodies; a contact... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070078919 - Multi-touch hand position offset computation: Apparatus and methods are disclosed for simultaneously tracking multiple finger and palm contacts as hands approach, touch, and slide across a proximity-sensing, multi-touch surface. Identification and classification of intuitive hand configurations and motions enables unprecedented integration of typing, resting, pointing, scrolling, 3D manipulation, and handwriting into a versatile, ergonomic computer... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.

20070078920 - Microprocessor with selectively available random number generator based on self-test result: A microprocessor including a random number generator within its instruction set architecture and made selectively available to program instructions of the instruction set architecture depending upon results of a self-test of the random number generator performed is disclosed. The microprocessor also includes a self-test unit that performs the self-test in... Agent: Huffman Law Group, P.C.

20070078921 - Fast dct algorithm for dsp with vliw architecture: A single stage computation method to perform a discrete cosine transform operation is provided. The discrete cosine transform operation is performed by executing a plurality of very large instruction words (VLIW) using a digital signal processor. The plurality of very large instruction words includes a first number of multiplications and... Agent: Qualcomm Incorporated

20070078922 - Determination apparatus and determination method: To provide a determination apparatus and a determination method which are capable of determining whether a signal outputted from a testing object is good or not, a CRC calculation circuit unit performs calculation on an image signal and a determination circuit unit compares a calculation result obtained by the CRC... Agent: Patrick G. Burns, Esq. Greer, Burns & Crain, Ltd.

20070078923 - Floating-point processor with selectable subprecision: A floating-point processor with selectable subprecision includes a register configured to store a plurality of bits in a floating-point format, a controller, and a floating-point mathematical operator. The controller is configured to select a subprecision for a floating-point operation, in response to user input. The controller is configured to determine... Agent: Qualcomm Incorporated