Electrical computers: arithmetic processing and calculating inventions 12/06

20060294168 - Apparatus and method of posting a sign on a crossbar: A sign sleeve includes a hollow cylinder that conformingly fits around a crossbar. Two opposing side flaps can be opened for draping the cylinder over the crossbar and thereafter fastened to close the cylinder. An exposed face of the cylinder bears sign indicia. Preferably the cylinder is formed from a... Agent: Thomas J. Tighe & Associates

20060294169 - System and method for eliminating common subexpressions in a linear system: A method for reducing operations in a processing environment is provided that includes generating one or more binary representations, one or more of the binary representations being included in one or more linear equations that include one or more operations. The method also includes converting one or more of the... Agent: Baker Botts L.L.P.

20060294170 - Diversity receiver device: A diversity receiver device includes N antennas to receive OFDM signals, N digital filters to filter the signals received by the N antennas in order to reduce delay spread, K (K≦N) beamforming units configured to subject the filtered signals to a beamforming process by using combining weights, an eigen-decomposition unit... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060294171 - Method and apparatus for video encoding and decoding using adaptive interpolation: A method and apparatus is disclosed herein for video encoding and/or decoding using adaptive interpolation is described. In one embodiment, the decoding method comprises decoding a reference index; decoding a motion vector; selecting a reference frame according to the reference index; selecting a filter according to the reference index; and... Agent: Blakely Sokoloff Taylor & Zafman

20060294172 - Method and system for high fidelity idct and dct algorithms: In a data processing system, a method and system employing high fidelity inverse discrete cosine transform (IDCT) and discrete cosine transform (DCT) algorithms are provided. The values of the coefficients in a two-dimensional (2D) transform utilized in the IDCT and DCT algorithms may approximate the ideal integer output with sufficient... Agent: Mcandrews Held & Malloy, Ltd

20060294173 - Implementation of a transform and of a subsequent quantization: The invention relates to an approximation of a DCT and a quantization which are to be applied subsequently to digital data for compression of this digital data. In order to improve the transform, it is proposed to simplify a predetermined transform matrix to require less operations when applied to digital... Agent: Perman & Green

20060294174 - Hardware-based cabac decoder: A method of decoding a stream of compression-encoded image data. The method includes supplying at least two values to an adder. At least one of the values is determined based at least in part on a type of a current syntax element in the stream of compression-encoded image data. The... Agent: Buckley, Maschoff, Talwalkar LLC

20060294175 - System and method of counting leading zeros and counting leading ones in a digital signal processor: A system and method is disclosed and includes an execution unit that can be used to count the leading zeros in a data word. During operation, the execution unit can receive a data word that has a width of 2 to the Nth power. Further, the execution unit can sign... Agent: Qualcomm Incorporated

20060294176 - Customizable information processing apparatus: An information processing apparatus of the invention includes an execution engine 120 activated on a browser, an application browser 130, and parts 131a and 132b. The execution engine 120 reads a flow definition 14 described in XML and sequentially executes commands defined by tags included in the flow definition 14.... Agent: Mcdermott Will & Emery LLP

20060294177 - Method, system and apparatus of performing division operations: Embodiments of the present invention provide a method, apparatus and system of dividing a first number by a second number. Some demonstrative embodiments include generating a first value relating to the first number; generating a second value corresponding to a remainder of a division of the number one by the... Agent: Pearl Cohen Zedek Latzer, LLP

20060294178 - Carry-ripple adder: A carry-ripple adder having inputs for supplying three input bits of equal significance 2n that are to be summed and two carry bits of equal significance 2n+1 that are also to be summed. A calculated sum bit of significance 2n and two calculated carry bits of equal significance 2n+1 which... Agent: Brinks Hofer Gilson & Lione Infineon

20060288060 - Method for looking up a table for data transferring and look-up table therewith: P

20060288061 - Smaller and faster comparators: Adder units are used to compare two numbers. A first logic unit receives one or more bits from a first number and the bits from a second number less the least significant bit of that second number. A second logic unit receives one or more bits from the second number... Agent: Fish & NeaveIPGroup

20060288059 - Synchronous counting circuit: A M by N bit synchronous counter for use in advanced applications is provided. The M by N bit synchronous counter comprises an M by N register configured to receive and store data corresponding to at least one word integrated with a N bit counter configured to sequentially count out... Agent: Hewlett Packard Company

20060288062 - Quantum random number generators: Disclosed is an all-fiber optical quantum random number generator, an optical coupler having an input port and two output ports; a single photon source connected to the input port, emitting a single photon which is transmitted from the input port to the output ports; a single photon detector connected to... Agent: Darby & Darby P.C.

20060288065 - Method and apparatus for lapped transform coding and decoding: A method, apparatus, and article of manufacture for deriving and using non-linearly adapted lapped transforms (NALTs) In one embodiment, the method comprises receiving parameters of a statistical fit between local statistics of original and processed frame data, determining adaptation parameters for application of an inverse lapped transform to frame data,... Agent: Blakely Sokoloff Taylor & Zafman

20060288063 - Method and system for high speed precoder design: Methods and systems for processing a signal are disclosed herein and may comprise adding a plurality of offsets to a summed input signal to generate a plurality of offset summed input signals. The offset summed input signals may be filtered to generate a plurality of filtered offset summed input signals.... Agent: Mcandrews Held & Malloy, Ltd

20060288064 - Reduced complexity recursive least square lattice structure adaptive filter by means of estimating the backward and forward error prediction squares using binomial expansion: A method for reducing a computational complexity of an m-stage adaptive filter is provided by expanding a weighted sum of forward prediction error squares into a corresponding binomial expansion series, expanding a weighted sum of backward prediction error squares into a corresponding binomial expansion series, and determining coefficient updates of... Agent: Brinks Hofer Gilson & Lione

20060288067 - Reduced complexity recursive least square lattice structure adaptive filter by means of approximating the forward error prediction squares using the backward error prediction squares: A method for reducing a computational complexity of an m-stage adaptive filter is provided by determining a weighted sum of backward prediction error squares for stage m at time n, determining a conversion factor for stage m at time n, inverting the weighted sum of backward prediction error squares, and... Agent: Brinks Hofer Gilson & Lione

20060288066 - Reduced complexity recursive least square lattice structure adaptive filter by means of limited recursion of the backward and forward error prediction squares: A method for reducing a computational complexity of an m-stage adaptive filter is provided by updating recursively forward and backward error prediction square terms for a first portion of a length of the adaptive filter, and keeping the updated forward and backward error prediction square terms constant for a second... Agent: Brinks Hofer Gilson & Lione

20060288068 - Memory control method for storing operational result data with the data order changed for further operation: An FFT operational device includes memory banks, an FFT operational circuit, and an FFT memory control circuit. The memory banks can overwrite pieces of data to specified address locations simultaneously or read out the data from the locations simultaneously. The operational circuit receives operands read out from the banks simultaneously... Agent: Nixon Peabody, LLP

20060288070 - Digital signal processing circuit having a pattern circuit for determining termination conditions: A method for detecting a pattern from an arithmetic logic unit (ALU) in an integrated circuit. The method includes the steps of: generating an output from an ALU; bitwise comparing the ALU output to a pattern to produce a first output; inverting the pattern and comparing the ALU output with... Agent: Xilinx, Inc Attn: Legal Department

20060288069 - Digital signal processing circuit having a simd circuit: An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the ALU has a plurality of adders,... Agent: Xilinx, Inc Attn: Legal Department

20060282486 - Electronic calculating hand held implement: An hand held implement which includes an integral preprogrammed electronic calculator. The implement is preset to perform one or more calculations which utilize known scientific formulas and mathematical relationships and which rely upon specific variables for which values are input by the user through the use of the various input... Agent: The Soni Law Firm

20060282487 - Method and system for pipelining saturated accumulation and other loops with loop-carried dependencies: Aggressive pipelining allows Field Programmable Gate Arrays (FPGAs) to achieve high throughput on many Digital Signal Processing applications. However, cyclic data dependencies in the computation can limit pipelining and reduce the efficiency and speed of an FPGA implementation. Saturated accumulation is an important example where such a cycle limits the... Agent: Alessandro Steinfl, Esq. C/o Ladas & Parry

20060282488 - Methods and systems for efficient filtering of digital signals: A method in a signal processor for filtering samples in a digital signal is provided. An approximate filtered sample is generated as a function of less than four samples of the digital signal. A correction is generated as a function of the less than four samples, and a filtered sample... Agent: General Instrument Corporation Dba The Connected Home Solutions Business Of Motorola, Inc.

20060282489 - Hardware function generator support in a dsp: The present invention relates to digital signal processors with an integrated module configured to compute a Coordinate Rotation Digital Computer (CORDIC) in a pipeline. The pipelined module can advantageously complete computation of one CORDIC computation for each clock pulse applied to the CORDIC module, thereby providing a CORDIC computation for... Agent: Patentmetrix

20060282490 - Precision complex sinusoid generation using limited processing: A first phasor associated with an electronic signal and a delta phasor associated with a cyclic rate of the electronic signal are multiplied to produce a second phasor. To compensate for any deviation in the magnitude of the second phasor, a real and imaginary correction factor are determined and added... Agent: Berkeley Law & Technology Group

20060282491 - Method for countermeasuring by masking the accumulators in an electronic component while using a public key cryptographic algorithm: The invention relates to a method for countermeasuring in an electronic component while using a public key cryptographic algorithm. The invention is characterized in that the method comprises an exponentiation calculation with a left-to-right exponentiation algorithm y=gˆd, in which g and y are elements of the specified group G noted... Agent: Buchanan, Ingersoll & Rooney PC

20060282492 - Determining mutual inductance between intentional inductors: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for example, circuit design information indicative of a first inductor and a second inductor is received. A dipole moment associated with the first inductor is determined, where the magnetic field associated with the... Agent: Klarquist Sparkman, LLP

20060277231 - Integrated software development and porting system for wireless devices: An integrated computer system and a method for developing a source code and for generating executable computer programs to be run on multiple wireless devices are provided. A computer system includes a wireless device selector, a universal and concurrent emulator, a build and porting engine, a resource manager, and a...

20060277232 - Small form-factor keyboard using keys with offset peaks and pitch variations: A small form-factor keyboard or keypad for key structures is provided in which individual key structures have a contact surface on which there is a center reference and a peak. The center reference and the peak or offset, so that an offset distance between the center reference and the peak...

20060277233 - Functionality disable and re-enable for programmable calculators: A handheld calculator with disable/re-enable capability. The calculator includes a keypad, a display screen, and circuitry internal to the calculator. The circuitry includes a microprocessor, a storage unit for storing data and programs for execution by the microprocessor to implement calculator functions. The storage unit has stored therein a disable/re-enable...

20060277234 - A compact processor element for a scalable digital logic verification and emulation system: A logic simulation acceleration processor optimized for multi-value logic level simulation of electronic systems described in hardware description languages....

20060277235 - Performing variable and/or bitwise shift operation for a shift instruction that does not provide a variable or bitwise shift option: Some embodiments present a method of performing a variable shift operation. This method can be used by a microprocessor that does not allow variable shift operation for certain operand sizes. The method simulates a shift instruction that shifts an operand by a shift count. The method identifies a first shift...

20060277236 - Multi-code correlation architecture for use in software-defined radio systems: A reconfigurable multi-code correlation unit for correlating a sequence of chip samples comprising 1) a memory for storing the chip samples; 2) a plurality of add-subtract cells, each add-subtract cell receiving a plurality of real bits, a, and a plurality of imaginary bits, b, from a first chip sample and...

20060277238 - Method and device for converting the sampling frequency of a digital signal: r

20060277237 - Nonlinear conversion system using precision mapping and the method thereof: A nonlinear conversion system using precision mapping and the method thereof are described. The system includes a source value converter, a mapping table unit, a recovering parameter computing unit, and an output computing unit. The method includes the steps of: receiving an input value; converting the input value into a...

20060277239 - Process of security of an unit electronic unit with cryptoprocessor: The invention concerns a process for securing an electronic device incorporating a hardware component capable of autonomous implementation of calculation process f using one key K, the process involves calculating at least two new keys K′j such that at least one of said new keys is identical to key K,...

20060277240 - Apparatus and method for implementing efficient arithmetic circuits in programmable logic devices: Efficient implementation of arithmetic circuits in programmable logic devices by using Look-Up Tables (LUTs) to store pre-calculated values. A table look-up operation is performed in place of complex arithmetic operations. In this way, at the expense of a few LUTs, many logic elements can be saved. This approach is particularly...

20060277241 - Apparatus and method for performing efficient multiply-accumulate operations in microprocessors: An apparatus for performing multiply-accumulate operations in a microprocessor comprising operand input registers for receiving data to be operated on an adder and a multiplier for performing operations on the data, a result output port for presenting results to the microprocessor, a multiplexer for storing results, an accumulator cache for...

20060277242 - Combining circuitry: A combining circuit and method combines a plurality of terms in a multiplier circuit. The combining circuit includes a first circuit, arranged to receive a first set of the plurality of terms and to combine the first set of terms to produce a first combined term set. The combining circuit...

20060277243 - Alternate representation of integers for efficient implementation of addition of a sequence of multiprecision integers: A technique for summing a series of integers of the form ii+i2+i3+ . . . in includes calculating the vector sum of the integers and a vector carry indicative of overflows resulting from generation of the vector sum. The vector sum and vector carry are used to calculate the sum...

20060277244 - Method and apparatus for formatting numbers in microprocessors: An apparatus for scaling numbers comprises register means for storing an operand to be scaled, bit shifting means for performing a right shift operation on the operand, rounding means, and decision means to test for the existence of at least one of an overflow and an underflow condition....

20060277246 - Multiplication circuitry: A multiplier circuit multiplies a first and a second operand. The circuit includes a sectioning circuit arranged to section the first operand into a first number of parts and a multiplier arranged to receive the second operand and a second number of the first number of parts. The multiplier is...

20060277245 - Multiply-accumulate unit and method of operation: An arithmetic unit for selectively implementing one of a multiply and multiply-accumulate instruction, including a multiplier, addition circuitry, a result register, and accumulator circuitry. The multiplier arranged to receive first and second operands and operable to generate multiplication terms. The addition circuitry for receiving multiplication terms from the multiplier and...

20060277247 - Hybrid arithmetic logic unit: Methods and apparatus for improving the efficiency of an arithmetic logic unit (ALU) are provided. The ALU of the invention combines the operation of a single-cycle ALU with the processing speed of a pipelined ALU. Arithmetic operations are performed in two stages: a first stage that produces separate sum and...