Electrical computers: arithmetic processing and calculating inventions 10/06

20060242213 - Variable precision processor: Systems and methods for processing variable precision data using tags to identify the positions of digits within data words. One embodiment comprises a processor having internal structures that are configured to represent a variable precision data word as a variable number of digits, where each digit includes a digit value...

20060242214 - Periodicity judgement apparatus, periodicity judgement method and periodicity judgement program: There is provided a periodicity judgment apparatus 100 to judge periodicity of time series data. A reception unit 206 receives the time series data and a set value of a period. A DFT transform unit 216 performs a Fourier transform of the time series data to obtain a Fourier coefficient...

20060242215 - Circuit for selectively providing maximum or minimum of a pair of floating point operands: A floating point max/min circuit for determining the maximum or minimum of two floating point operands includes a first analysis circuit configured to determine a format of a first floating point operand of the two floating point operands based upon floating point status information encoded within the first floating point...

20060242216 - Method and an electrical device for efficient generation of multi-rate pseudo random noise (pn) sequence: An electrical device for generating a multi-rate pseudo random noise (PN) sequence. A sequence generator is adapted to output a plurality of sequence values based on a step control signal (St). A selection system is adapted to select one of a plurality of sequence values based on a select value...

20060242217 - Sampling method: The present invention is an incremental umbrella sampling method to improve the performance of established sampling methods. It is sampling the state space by iteratively generating states xi,t and their weighting factors represented by Formula (a) by fitting the sampling distribution function ρj(x) of the next iteration to at least...

20060242218 - Prior-constrained mean shift analysis: A system and method are provided for prior-constrained mean shift analysis of a data array, the system including a processor, an input adapter in signal communication with the processor for receiving at least one data array, and a prior constraints unit in signal communication with the processor for performing a...

20060242219 - Asynchronous multiplier: An asynchronous multiplier is provided. The multiplier comprises a partial product generator, an addition array, a leading-zero-bit detector, a final-stage adder and a completion detector. The partial product generator generates a plurality of partial products, and the addition array adds these partial products. The leading-zero-bit detector detects effective bits of...

20060242220 - Hardware divider: Systems and methods are provided for dividing two digital values. A look-up table provides a first output value in response to a value of an input signal. The first output value corresponds to a first estimate of a reciprocal for the value of the input signal. An approximation component provides...

20060242221 - Data value addition: A data processing apparatus operable to sum data values said data processing apparatus comprising: a plurality of adder logic stages arranged in parallel with each other; control logic operable in response to receipt of a request to sum two data values to forward portions of said two data values to...

20060235911 - Contemporaneous symbolic and numeric presentation: A piece of software running on either a computer or a calculator for receiving a mathematical expression is described. The mathematical expression is evaluated to obtain its symbolic result. If the symbolic result can be resolved to its numeric result, the software executes to obtain the numeric result. The software...

20060235912 - Displaying variables stored in calculators: A centralized view and management of stored variables for calculators and pieces of software emulating calculators is provided. Users can glance at the status bar and know what variables are stored. A single click then brings up a window within which a list of the stored variables and their values...

20060235914 - Method and apparatus for providing packed shift operations in a processor: A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent...

20060235913 - Software product for processing user interfaces of digital device and method for processing user interfaces: Disclosed is a user interface processing software architecture of a digital device. The user interface processing software architecture of a digital device provides software that can effectively process complicated events created by various user interfaces or the like of a functionally complex digital device. To this end, the software architecture...

20060235915 - Method and apparatus for converting data, method and apparatus for inverse converting data, and recording medium: A data converting apparatus includes a segmenting unit for setting a predetermined access unit, as an access unit to be processed, out of input data containing at least one access unit containing a plurality of data components per pixel, and for segmenting the access unit to be processed into at...

20060235916 - System of converting information words to a signal: A method of converting m-bit information words to a runlength constrained modulated signal is described. The available code words are distributed over at least one group (G1) of a first type and at least one group (G2) of a second type. The delivery of a code word belonging to the...

20060235917 - Systems and methods for generating random numbers from astronomical events: The invention discloses systems and methods for generating pure random numbers from astronomical events, such as cosmic radiation or solar events. The invention includes a detector, a logic circuit, memory, power supply and a communication device. The detector may be, for example, a solar wind particle detector, an alpha ray...

20060235918 - Apparatus and method to form a transform: An apparatus, in some embodiments, includes a one-port memory and a transform unit coupled to the one-port memory. A method, in some embodiments, includes interleaving reading data points for a first data signal from a memory location with writing data points for a second data signal to the memory location,...

20060235919 - Optimizing detector target polynomials in read/write channels to achieve best error rate performance in disk drives: Embodiments of the invention provide techniques for optimizing the detector target polynomials in read/write channels to achieve the best error rate performance in recording devices. In one embodiment, a method of obtaining a detector target polynomial of a read/write channel to achieve best error rate performance in a recording device...

20060235920 - Smart evaluation in computer algebra: In a computing system, evaluating a mathematical expression in presented hierarchically according to the rules of precedence of operations, initial operations at the bottom of the hierarchy may yield values too large to be calculated conventionally, even if the ultimate value of the expression may represent a calculable value. The...

20060235921 - Device and method for calculating conversion parameter of montgomery modular multiplication and program therefor: A method for calculating a conversion parameter of the Montgomery modular multiplication to improve the efficiency of software installation, comprising a first step for calculating H0=2v×R (mod n) (where v is an integer, v≧1, and (m×k)/v is an integer), a second step for calculating Hp=2v×2p×R (mod n) from H0=2v×R (mod...

20060235922 - Quisquater reduction: A method and apparatus for calculating the product P of a first number X and a second number Y, modulo N, where Y is partitioned into j words each of length p bits, and has a length (m+n) bits, cyclically operates on successive ones of the j words of Y,...

20060235923 - Carry-ripple adder: A carry-ripple adder has four summing inputs for receiving four input bits having the significance w that are to be summed, three carry inputs for receiving three input carry bits having the significance w, a summation output for outputting an output summation bit having the significance w, and three carry...

20060235924 - Electronic circuit: An electronic circuit for performing logic operations is provided. The electronic circuit comprises a logic gate having at least two binary inputs adapted to receive corresponding input binary digits; an output for outputting an output signal; signal transmission means between said input and said output; a logic circuit coupled to...

20060230088 - Shift register circuit: The present invention discloses a shift register circuit, comprising a plurality of shift register units and a switching circuit. The shift register units are electrically connected in series. The switching circuit electrically connects to the shift register units to divide the shift register units into a first group of shift...

20060230089 - Frequency estimation: The present invention relates to a method and hardware for estimating the frequency offset of a signal. The method includes obtaining samples of the signal at at least two instants in time, and utilising the samples in a mathematical equation relating estimated offset frequency to the samples, wherein the mathematical...

20060230090 - Integrated lifting wavelet transform: The integrated lifting transform provides both the lossy and lossless lifting wavelet transforms while sharing the same lifting chain for either lossy data compression or lossless data compression. The lifting steps can provide a lossless compression and a lossy compression directly from lossless compression while the integer-to-integer adaptive four-stage lifting...

20060230091 - Method and apparatus for compressing image data: The present invention provides a method of compressing image data. The method includes a step of transforming image data into data composed of frequency components. In the transforming step, a number of bits calculated for frequency components requiring relatively low calculation quality for a transforming process is reduced below a...

20060230092 - Architectural floorplan for a digital signal processing circuit: A physical floorplan for a digital signal processing (DSP) block including; an interconnect column having a plurality of programmable interconnect elements; a first DSP element having a plurality of first columns, a first output register column of the plurality of first columns positioned adjacent to the interconnect column; and a...

20060230093 - Digital signal processing circuit having a pattern detector circuit for convergent rounding: An integrated circuit (IC) for convergent rounding including: an adder circuit configured to produce a summation; a comparison circuit configured to bitwise compare the summation with an input pattern, bitwise mask the comparison using a mask, and combine the masked comparison to produce a comparison bit; and rounding circuitry for...

20060230094 - Digital signal processing circuit having input register blocks: An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE adjacent to the top DSPE having a third and a fourth register block coupled to a second ALU circuit,...

20060230095 - Digital signal processing circuit having a pre-adder circuit: A digital signal processing circuit having a pre-adder circuit includes; a first register block and a pre-adder circuit coupled to a multiplier circuit and to a set of multiplexers, where the set of multiplexers are controlled by an opcode, and where the pre-adder circuit has a first adder circuit; and...

20060230096 - Digital signal processing circuit having an adder circuit with carry-outs: An integrated circuit having a digital signal processing (DSP) circuit is disclosed. The DSP circuit includes: a plurality of multiplexers receiving a first set, second set, and third set of input data bits, where the plurality of multiplexers are coupled to a first opcode register; a bitwise adder coupled to...

20060230097 - Process model monitoring method and system: A computer-implemented method is provided for monitoring model performance. The method may include obtaining configuration information and obtaining operational information about a computational model and a system being modeled. The computational model and the system may include a plurality of input parameters and one or more output parameters. The system...

20060224645 - Bio-metric input mechanism: A biometric keyboard or other input device, such as a keypad or touch screen, may be part of an input mechanism for inputting user information to a computing system. The mechanism may include biometric sensors associated with the buttons or keys of the input device. A mapping scheme may be...

20060224644 - System(s), method(s), and apparatus for detecting end of slice groups in a bitstream: Presented herein are system(s), method(s), and apparatus for detecting end of slice groups in a video bitstream. In one embodiment, there is presented a circuit for extracting a data structure from one or more data words. The circuit comprises a multiplexer, a bit pointer, a first logic circuit, and a...

20060224646 - System (s), method (s), and apparatus for converting unsigned fixed length codes (decoded from exponential golomb codes) to signed fixed length codes: Presented herein are system(s), method(s), and apparatus for converting unsigned fixed length codes to signed fixed length codes. In one embodiment, there is presented a circuit for converting an unsigned code to a signed code. The circuit comprises a multiplexer. The multiplexer comprises a first input, a second input, and...

20060224647 - Rfid tag using updatable seed values for generating a random number: Apparatus and method for generating random numbers in an RFID tag circuit. The RFID tag circuit includes a random number generator (RNG) operable to output a random number based on a seed value and further includes a non-volatile memory (NVM) register operable to store an updatable seed value that is...

20060224648 - Method and apparatus for providing a base-2 logarithm approximation to a binary number: An apparatus for providing a base-2 logarithm approximation to a binary number is disclosed. A position k of the most significant bit within a binary number is located. Then, all bits that are less significant than position k within the binary number are assigned as a fractional portion of a...

20060224649 - Interpolation and decimation using newton polyphase filters: An interpolation filter for interpolating a digital signal includes a cascade of template filters, each having an identical template transfer function A(z), which is arranged to receive and filter an input sequence representing the digital signal sampled at an input sampling rate. Ancillary circuitry is coupled to the cascade so...

20060224650 - Fast fourier transform processing in an ofdm system: An FFT processor for an OFDM receiver includes multiple interrelated operational blocks. The FFT processor is configured to perform data demodulation, channel estimation, and fine timing acquisition on received OFDM symbols. The FFT processor incorporates a pipelined FFT engine using a memory architecture shared with channel estimation and demodulation blocks....

20060224651 - Combined ifft and fft system: A system (12) for determining discrete transforms as between time and frequency domains. The system comprises a grid (60) comprising adders and multipliers. The grid is operable to perform in parallel an integer number P operations of a first transform function selected from one of either an IFFT or an...

20060224652 - Instruction set processor enhancement for computing a fast fourier transform: This invention describes a method of computing a fast Fourier transform (FFT) using enhanced processor computational capabilities for more efficient and flexible implementation of an electronic device (e.g., a linear equalizer) based on that FFT computing. A simple non-parallel instruction set processor (or just a non-parallel processor) containing complex multiplication...

20060224653 - Method and system for dynamic session control of digital signal processing operations: A method and system for performing digital signal processing operations in a computer system are disclosed. In addition to the ability to perform DSP operation on a new hardware platform, this method and system allow the dynamic and global control of saturation and left shifting prior to accumulation....

20060224654 - Method and system for performing digital signal processing operations in a computer system: A method and system for performing digital signal processing operations in a computer system are disclosed. Digital Signal Processing operations such as multiply and add (MADD) or multiply and subtract (MSUB) can be performed by general-purpose microprocessors. The DSP operations are directed to n-bit operands that are in m-bit registers....

20060224655 - Apparatus for estimating direction of arrival wave: Apparatus has means for computing correlation matrix of arrival wave, means for producing a matrix for obtaining eigenvalues and a matrix for obtaining eigenvectors, means for computing column norms on the matrix which is a subject for Householder transformation, means for judging whether a maximum value of the column norms...

20060224656 - Methods and apparatus for efficient complex long multiplication and covariance matrix implementation: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance...

20060224657 - Method, system and apparatus for quotient digit generation: Embodiments of the present invention provide a method, apparatus and system to generate a quotient digit corresponding to a quotient of a cycle of a division operation by applying a predetermined criterion to a plurality of expected partial remainder values related to a plurality of possible quotient digits Other embodiments...

20060224658 - Sample analyzing method and sample analyzing device: This invention relates to a technique for analyzing a sample. A sample analyzer (1) provided by the invention includes: a voltage applier (12) for applying a voltage to a reaction field which includes a sample; a response measurer (13) for measurement of a response to the voltage applied to the...