Electrical computers: arithmetic processing and calculating inventions 08/06

20060195494 - Compiler, system and method for defining, assigning, executing and monitoring processes and tasks in process management applications: The invented software system and method is an easy-to-use, browser-based solution, providing casual business computer users the ability to create, modify, and monitor business processes, much like spreadsheet software allows users to quickly complete complex math calculations. It is built on a “fill in the table” interface so any user...

20060195495 - Information processing system reducing inconvenience relating to distance between computer and printer or the like: An information processing system includes a device having a printing unit and an information processing apparatus connected to the device via a network. The device includes a display screen sharing client unit configure to acquire data of a display screen displayed at the information processing apparatus and to display the...

20060195496 - Digital signal processing circuit having a pattern detector circuit: An integrated circuit for pattern detection including: an arithmetic logic unit coupled to a comparison circuit, where the arithmetic logic unit is programmed by an opcode; a selected pattern of a plurality of patterns selected by a first multiplexer, where the first multiplexer is coupled to the comparison circuit; and...

20060195497 - Method, apparatus and program storage device that provides a shift process with saturation for digital signal processor operations: A method, apparatus and program storage device that provides a shift process with saturation for digital signal processor operations are disclosed. An instruction is generated for shifting an operand to either maximum or the minimum value depending on the bit of data input when saturation occurs. A saturation detection circuit...

20060195498 - Digital filter instruction and filter implementing the filter instruction: A digital filter instruction and filter implementing the filter instruction are disclosed. The filter instruction synthesizes a digital filter and includes an instruction field, a tap length field, a coefficient address field, a data header address field, a clear accumulator bit and an update bit. The filter instruction a concise...

20060195499 - Method for optimization of q-filter kernel parameters: A Q-Filter is a reconfigurable technique that performs a continuum of linear and nonlinear filtering operations. It is modeled by unique mathematical structure, utilizing a function called the Q-Measure, defined using a set of adjustable kernel parameters to enable efficient hardware and software implementations of a variety of useful, new...

20060195500 - Determination of a common fundamental frequency of harmonic signals: Techniques are provided for determining the time course of the fundamental frequency of harmonic signals, wherein the input signal is split into different frequency channels by band pass filters. Distances between crossings of different orders are determined, and a histogram of all these distance values for each instant in time...

20060195501 - Method and system for noise measurement with combinable subroutines for the mesurement, identificaiton and removal of sinusoidal interference signals in a noise signal: A method combines, within a system for noise measurement, subroutines for the measurement, identification and removal of sinusoidal interference signals (Ak·ej(ωkt+φk), Ak·ej(μ·ωkΔt+φk)) in a noise signal (w(t), w(ν·Δt)). In this context, the procedural stage (S10, S110, S220) of splitting the frequency range (ν) to be measured into several frequency bands...

20060195502 - Group delay compensation using ifft filters: A method, computer program, and apparatus for compensating for group delay. The method comprises the steps of generating a raw step response of a system, differentiating the raw step response to generate an impulse response of the system, windowing the impulse response and taking a Fast Fourier Transform (FFT) of...

20060195503 - Integrated circuit including at least one configurable logic cell capable of multiplication: The present invention provides an integrated circuit including at least one configurable logic cell capable of multiplication comprising an addition means for adding a first input and a partial product; a first multiplexing means for receiving a first output of said addition means at its first input and said partial...

20060190511 - Electrical power multiplication: A power multiplier and method are provided. The power multiplier includes a power multiplying network that is a multiply-connected, velocity inhibiting circuit constructed from a number of lumped-elements. The power multiplier also includes a launching network, and a directional coupler that couples the launching network to the power multiplying network....

20060190512 - Electrical power multiplication: A power multiplier and method are provided. The power multiplier includes a power multiplying network that is a multiply-connected, velocity inhibiting circuit constructed from a number of lumped-elements. The power multiplier also includes a launching network, and a directional coupler that couples the launching network to the power multiplying network....

20060190513 - Use of electrical power multiplication for power smoothing in power distribution: A system for power smoothing in power distribution and methods are provided. In one embodiment, a power multiplying network is provided that comprises a multiply-connected, velocity inhibiting circuit constructed from a number of lumped-elements. The power multiplying network is coupled to a power distribution network. The power multiplying network is...

20060190514 - Data processing apparatus: A data processing apparatus comprises a plurality of calculating units connected each other in series, a plurality of memories connected in between the plurality of calculating units, and a control unit operable to determine a calculating unit, which performs calculation in a unit cycle, among the plurality of the calculating...

20060190515 - Lookup table and data acquisition method: Input data is divided into a plurality of blocks, and the blocks are corresponded to each address of the lookup table, and a block is divided into a plurality of sections according to the change of the output data, and at this time position information to indicates the boundary of...

20060190516 - Digital signal processing element having an arithmetic logic unit: A digital signal processing circuit including: a multiplier circuit; a plurality of. multiplexers coupled to the multiplier circuit and controlled by a first opcode; and an arithmetic logic unit coupled to plurality of multiplexers and controlled by a second opcode....

20060190517 - Techniques for transposition of a matrix arranged in a memory as multiple items per word: A system, apparatus, method and article to perform transposition of a matrix arranged in memory as multiple items per word are described. The apparatus may include a media processing node to process media information. The media processing node may include a memory to store the media information as a matrix...

20060190518 - Binary polynomial multiplier: A multiply unit includes support for arithmetic operations, binary polynomial operations, and permutations....

20060190519 - Extended precision accumulator: A multiply unit includes an extended precision accumulator. Microprocessor instructions are provided for manipulating portions of the extended precision accumulator including an instruction to move the contents of a portion of the extended accumulator to a general-purpose register (“MFLHXU”) and an instruction to move the contents of a general-purpose register...

20060190520 - Analog filter: An analog filter includes a first arithmetic operation section 2-1 having a plurality of sets of processing circuit being cascade connected, each processing circuit having an S/H circuit of plural stages for holding a ΔΣ-modulated signal and an analog adder for adding the input and output signals of the S/H...

20060184593 - Multi-cover device: A multi-cover device positioned on a main body is disclosed. The multi-slide device includes an outer cover, an inner cover disposed on the main body and positioned inside the outer cover, and a latch device positioned between the inner cover and the outer cover for controlling the outer cover to...

20060184594 - Data processing apparatus and method for determining an initial estimate of a result value of a reciprocal operation: The present invention provides a data processing apparatus and method for generating an initial estimate of a result value that would be produced by performing a reciprocal operation on an input value. The input value and the result value are either fixed point values or floating point values. The data...

20060184595 - Representative majority voter for bus invert coding: In general, in one aspect, the disclosure describes an apparatus inluding a representative majority voter gate to analyze bit transitions of a pluraility of bits. The plurailuty of bits are analzed in groups. The representative majority voter gate generates an invert signal based on the analysis. The apparatus further inludes...

20060184596 - Fir filter device for flexible up-and downsampling: A FIR filter includes an input pipeline IP with a sequence of input delay cells DI; each for storing an input sample, and a plurality of N input tap points TP. An output pipeline includes a sequence of output delay cells DO; each for storing a sample, a plurality of...

20060184597 - Signal processing apparatus, signal processing method, and recording medium: A signal processing apparatus includes the following elements. A plurality of signal processing software modules perform unit signal-processing steps of signal processing by means of software processing. An instruction input receiving unit receives an instruction. A virtual connecting unit sets up a virtual connection between inputs and outputs of the...

20060184598 - Optimized discrete fourier transform method and apparatus using prime factor algorithm: An apparatus and method for DFT processing using prime factor algorithm (PFA) on a selected number P of midamble chip values received by a CDMA receiver, where P has a plurality M of relatively prime factors F, and the DFT process is divided into M successive F-point DFT processes. The...

20060184599 - Correlation architecture for use in software-defined radio systems: A re-configurable correlation unit for correlating a sequence of chip samples comprising: 1) a memory for storing the chip samples; 2) a plurality of add-subtract cells, each add-subtract cell receiving a plurality of real bits, a, and a plurality of imaginary bits, b, from a first chip sample; and 3)...

20060184600 - Residue number system arithmetic operating system, scaling operator, scaling operation method and program and recording medium of the same: There is provided a scaling operator for calculating a quotient in a first residue format obtained by dividing an input number in the first residue format by a second modulus in a residue number system for representing numbers by the first residue format of a set of residues obtained with...

20060184601 - Floating point unit with fused multiply add and method for calculating a result with a floating point unit: The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with...

20060184602 - Data processing apparatus and method for performing a reciprocal operation on an input value to produce a result value: A data processing apparatus and method are provided for performing a reciprocal operation on an input value d to produce a result value X. The reciprocal operation involves iterative execution of a refinement step to converge on the result value, the refinement step performing the computation: Xi=Xi−1*M, where Xi is...

20060184604 - Arithmetic unit: In order to correct an overflow of a multiplication result while improving the operation speed, an overflow detection unit detects an overflow based on whether a multiplicand A and a multiplier B are both a negative value with the largest absolute value. A carry-save adder adds together in carry-save addition...

20060184603 - Zero detect in partial sums while adding: The present invention relates to a method and circuit for performing multiply-operations in an arithmetic unit of a computer processor. In a multiplier thereof, zero detection of the resulting product bit string (22) is needed for a proper setting of condition code and overflow status information. Zero detection according to...

20060184605 - Method of forcing 1's and inverting sum in an adder without incurring timing delay: A summing circuit for an adder decodes control signals to determine that the result should be manipulated, and generates a half-sum output which is used to produce a manipulated result based on the control signals. The half-sum output is combined with a previous carry bit to complete the sum operation....

20060173942 - Method and system for prioritizing data values for robust data representation: Methods, systems and data structures select prioritized robust data values from a plurality of available data values formed by a plurality of data bits, each capable of exhibiting a bit value. Available data values are arranged into a gray code format, and alternate values of gray code format are selected...

20060173941 - Systems and methods for implementing logic in a processor: Systems, methods and media for implementing logic in the arithmetic/logic unit of a processor are disclosed. More particularly, hardware is disclosed for computing logical operations with minimal hardware by organizing the execution unit such that the propagate and generate functions required for the adder can be used as a basis...

20060173943 - Random number generator and method for generating random numbers: Random number generator including a first signal source outputting a first signal having a first frequency, a second signal source outputting a second signal having a second frequency which is lower than the first frequency, and time delay elements, wherein the output signals are delayed by a time interval with...

20060173944 - Exponential function generator: An exponential function generator for generating an exponential generator to realize a linear region of about 60 dB required for the an ultra wide band system (UWB). Since the exponential function generator is implemented in a form of complementary metal oxide semiconductor fabrication (CMOS), compactness and operation control of the...

20060173945 - Partial output finite impulse response filter: Apparatus and methods are provided to implement an efficient partial output finite impulse response (FIR) filter. In one embodiment, the filter operates by first receiving a set of samples from a streaming data source via a communications medium. Next the set of samples are organized into a convolution matrix which...

20060173946 - Common shift-amount calculation for binary and hex floating point: A method and system for performing a binary mode and hexadecimal mode Multiply-Add floating point operation in a floating point arithmetic unit according to a formula A*C+B, wherein A, B and C operands each have a fraction and an exponent part expA, expB and expC and the exponent of the...

20060173947 - Method and structure for a hybrid full-packed storage format as a single rectangular format data structure: A method (and structure) of linear algebra processing, includes processing a (real or complex) matrix data having elements originally stored in one of a triangular format and a symmetric matrix format in a subroutine designed to process matrix data in a full format. The processing uses a hybrid full packed...

20060173948 - Scalable 2x2 rotation processor for singular value decomposition: A two-plane rotation (TPR) approach to Gaussian elimination (Jacobi) is used for computational efficiency in determining rotation parameters. A rotation processor is constructed using the TPR approach to perform singular value decomposition (SVD) on two by two matrices yielding both eigenvalues and left and right eigenvectors. The rotation processor can...

20060173949 - Division arithmatic unit of variable radix: A variable radix divider uses dividend, divisor and quotient as division operators and includes an adder/subtractor having inputs of the dividend and the divisor. The divider further includes a first and second quotient/radix generator having inputs of the dividend and the divisor, a first multiplexer having input of the output...