Electrical computers: arithmetic processing and calculating inventions 07/06

20060167962 - Method and apparatus for improved direct digital frequency synthesizer: An improved DDFS includes a minority-bit detector to permit a series of cascaded transformation stages to perform half or less than half of the rotational operations otherwise required by detecting whether the required rotation or non-rotation operations are in the minority and performing only the operations in the minority. This...

20060167963 - Method and device for controlling a reproduction unit using a multi-channel signal: A method of controlling a sound field reproduction unit (2) having numerous reproduction elements (3n), uses a plurality of sound information input signals (SI) which are each associated with a general pre-determined reproduction direction which is defined in relation to a given point (5). The method includes: determining parameters which...

20060167964 - Methods and systems for a multi-channel fast fourier transform (fft): In at least some embodiments, a method is provided. The method includes receiving samples from a first input channel and a second input channel. The method further includes controlling commutators to selectively switch samples between the first and second input channels for input to a radix-2 butterfly. The method further...

20060161607 - Method and structure for cache aware transposition via rectangular subsections: A method and structure for transposing a rectangular matrix A in a computer includes subdividing the rectangular matrix A into one or more square submatrices and executing an in-place transposition for each of the square submatrices Aij....

20060161608 - Frequency converter using optical excitation surface plasma and its method: A frequency converter having no solid-state devices having nonlinear characteristics and no complex resonator structure and operable in a wide frequency range from microwave frequencies to terahertz wave frequencies. An input section (1) inputs an input wave into a high-frequency transmission line (2). A waveguide portion of an output section...

20060161609 - Method and system for saturating a left shift result using a standard shifter: A method for left shifting data includes left shifting the data to produce a left-shift result, right shifting the data to produce a right-shift result, and determining if the left-shift result requires saturation based on the right-shift result....

20060161610 - Device and method for generating a sequence of numbers: A random number generator for generating a sequence of numbers comprises a first shift register with a nonlinear feedback, a first number of memory cells and a first output coupled to the first number of memory cells by a first coupling means. Further, the number generator comprises a similarly constructed...

20060161611 - Device and method for determining a correlation maximum: A device for detecting a correlation maximum value from a sequence of correlation magnitude values includes a means for determining a reference value from correlation magnitude values within an interval of the sequence of correlation magnitude values, the correlation magnitude value to be assessed lying external to interval. A means...

20060161612 - Method and structure for a generalized cache-register file interface with data restructuring methods for multiple cache levels and hardware pre-fetching: A method and structure for executing a matrix algorithm requiring an order of N3 operations including data reformatting operations, where N is a dimension of an operand of said algorithm on a computer, includes initially reformatting data for at least one matrix used in the matrix algorithm into a data...

20060161613 - Method and apparatus for arithmatic operation of processor: A method and apparatus for arithmetic operation of a processor are disclosed. The method and apparatus divide operands whose wordlength is greater than the wordlength which can be processed by a processor once into wordlengths which can be processed by the processor and then perform operations therebetween. The method and...

20060161614 - N-bit constant adder/subtractor: An area efficient realization of an N-bit constant coefficient adder/subtractor implemented on FPGAs, utilizing N LUTs with single output generation capability. It includes three inputs from every LUT for addition/subtraction, without any requirement for extra logic for support of arithmetic mode and carry chains. For FPGAs supporting 4-input LUTs, the...

20060155793 - Canonical signed digit (csd) coefficient multiplier with optimization: An apparatus comprising an address generation circuit, a lookup table, a multiplexer and an output circuit. The address generation circuit may be configured to generate a series of addresses. The lookup table may be configured to generate one or more coefficients in response to the addresses. The multiplexer circuit may...

20060155794 - Reduced complexity idct decoding with graceful degradation: Data compressed according to a lossy DCT-based algorithm, such as the MPEG or MPEG2 algorithms, is decompressed according to a dynamically-selected set of DCT coefficients, with unused coefficients masked out. A macroblock of the data exhibiting little motion is decompressed with a small subset of DCT coefficients, while a macroblock...

20060155795 - Method and apparatus for hardware implementation of high performance fast fourier transform architecture: An high performance Fast Fourier Transform implementation in hardware is achieved through placement of a number of Butterfly/Dragonfly or “FLY” cells that run concurrently during a transformation process. The bank of FLY cells interacts according to FFT/IFFT algorithms through use of a resource-sharing fabric. The resource-sharing fabric allows the bank...

20060155796 - System and methods for large-radix computer processing: Systems and methods for performing large-radix numeric operations. A first number may be segmented into large-radix segments, wherein numbers of the segments are generated such that radix of the segment is greater than radix of the first number. As a result, a plurality of disparate processor-based computing systems may be...

20060155797 - Systolic squarer having five classes of cells: A systolic squarer comprises a systolic array classified into five cell modules by pipeline and regulation according to each operational circuit. According to fundamental structures, the five cell modules constitute the systolic squarer. Each of the cell modules is selected from a group consisting of plural full adders, plural half...

20060155798 - Eigenvalue decomposition and singular value decomposition of matrices using jacobi rotation: Techniques for decomposing matrices using Jacobi rotation are described. Multiple iterations of Jacobi rotation are performed on a first matrix of complex values with multiple Jacobi rotation matrices of complex values to zero out the off-diagonal elements in the first matrix. For each iteration, a submatrix may be formed based...

20060149801 - Method of encoding a signal into a bit stream: The invention relates to a method of encoding an input signal into an output bit stream (BS). Said method comprises steps of applying (1) a transformation to a block of values (BV) in order to get a transformed block (T), scanning (2) the coefficients (C1-C1) of a transformed block (TB)...

20060149802 - Scaling filter and method thereof: A scaling filter includes: two line buffers for buffering a plurality of pixel values corresponding to a plurality of source pixels, respectively; (N+1) multiplexers coupled to the line buffers for multiplexing the pixel values to output (N+1) intermediate values, respectively, wherein N is an integer; N bit shifters coupled to...

20060149803 - Multipurpose functional unit with multiply-add and format conversion pipeline: A multipurpose functional unit is configurable to support a number of operations including multiply-add and format conversion operations, as well as other integer and/or floating-point arithmetic operations, Boolean operations, and logical test operations....

20060149804 - Multiply-sum dot product instruction with mask and splat: An instruction, corresponding methods, and circuitry for efficiently performing partial dot sum products are provided. The instruction may include a source select field for specifying one or more source word elements to participate in the dot sum operation. The instruction may also include a target select field for specifying one...

20060149805 - Implementation of digital signal processing functions using maximal efficiency and minimal energy dissipation: Herein described is a method and system of implementing integrated circuit logic modules that provide maximum efficiency and minimum energy dissipation. In a representative embodiment, a method of implementing one or more digital signal processing functions comprises determining one or more parameters associated with generating an optimal logic module. The...