Electrical computers: arithmetic processing and calculating inventions 06/06

20060143257 - Efficient implementations of the threshold-2 function: A circuit and a method for operating the circuit are disclosed. A first step of the method generally comprises generating a plurality of first intermediate signals in two parallel first operations each responsive to a respective half of a plurality of input signals. A second step involves generating a plurality...

20060143258 - Fast fourier transform processor: A Fast Fourier Transform (FFT) processor is provided. It comprises a multiplexer, a first angle rotator, a second angle rotation and multiplexing unit, an adder, a twiddle factor storage, a multiplier, and a data storage. The FFT processor analyzes the input/output order of the Fast Fourier Transformation, separates the portions...

20060143259 - Low power vector summation method and apparatus: An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension...

20060143260 - Low-power booth array multiplier with bypass circuits: A low-power Booth array multiplier with bypass circuits is provided. The multiplier includes a first encoder for Booth-encoding the multiplier; a second encoder for pre-encoding the multiplier to generate an enabling signal and a plurality of control signals, wherein the control signals are used for determining whether to process partial...

20060143261 - Method and apparatus for performing a multiplication or division operation in an electronic circuit: A multiplication or division operation X·K or X·1/K is performed in an electronic circuit. A software circuit area of the circuit calculates a digit shift sv such that psv is an approximate value for K. In a hardware circuit area, the value X is shifted sv digits to the left...

20060136531 - Leading zero counter for binary data alignment: A method and apparatus are provided for aligning data in a binary word. A coded address is provided for each bit of the binary word. Each coded address is modified as a function of a logic state of the respective bit of the binary word to produce respective modified addresses....

20060136533 - Electric apparatus and method for game: An electric apparatus for a game includes a display unit, an operational unit, and an input unit. The display unit displays a mathematic expression including a plurality of parameters and corresponding values of the parameters. The operational unit calculates a correct answer of the mathematic expression. The input unit allows...

20060136532 - Light reflection intensity calculation circuit: A circuit for calculating a light reflected component with high accuracy. The circuit for calculating a reflected component of light reflected from an object having a rough surface comprises a means for storing the reflectance of an object in relation to the value φ or the value of cos φ,...

20060136534 - Method, system, and computer-readable medium for controlling the calculation of volatile functions in a spreadsheet: A method, system, and computer-readable medium are provided for controlling the calculation of volatile functions in a workbook created in a spreadsheet application program such that the volatile function does not need to be recalculated each time a calculation request is received in the workbook. A volatile function may include...

20060136535 - Method, system, and computer-readable medium for determining whether to reproduce chart images calculated from a workbook: A method, system, and computer-readable medium are provided for determining whether to reproduce a chart image from the contents of a spreadsheet application workbook on a server. A calculation server calculates chart data for defining a chart image from workbook data retrieved from the spreadsheet application workbook, generates a representation...

20060136536 - Data processing apparatus and method for converting a fixed point number to a floating point number: A data processing apparatus and method are provided for converting an m-bit fixed point number to a rounded floating point number having an n-bit significand, where n is less than m. The data processing apparatus comprises determination logic for determining the bit location of the most significant bit of the...

20060136537 - Phase persistent agile signal source method, apparatus, and computer program product: A phase persistent agile signal source method, apparatus, and/or computer program product provides a direct digital synthesizer (DDS) clock rate, provides a frequency tuning word (FTW) for a desired output frequency, provides a DDS update for a desired DDS update rate, provides an equivalent frequency least significant bit (LSB) for...

20060136538 - Calculating circuit and method for computing an n-th root and a reciprocal of a number: A calculating circuit and a method for generating an output signal representing an output number approximating an N-th root and/or a reciprocal of an input number represented by an input signal are described. The calculating circuit includes a subtractor circuit, an integrator circuit, and a multiplier circuit. The subtractor circuit...

20060136539 - Data processing device with microprocessor and with additional arithmetic unit and associated method: In order to further develop a data processing device (100; 100′) having at least one microprocessor (90) and having at least one additional arithmetic unit (40) as well as a method of performing at least one particular defined calculation by means of the data processing device (100; 100′) in such...

20060136540 - Enhanced fused multiply-add operation: An apparatus, method, and system for performing an enhanced fused multiply-add operation is disclosed. In one embodiment, an apparatus includes an exponent unit. The exponent unit includes a first adder to generate S1, where S1 is the sum of an integer k, the exponent of a floating point value A,...

20060136541 - Binary digit multiplications and applications: A multiplying system for binary digits. The digits are multiplied in a rectangular memory array, where the digits are placed along the edges, and intersections between 1's form blocks of 1's in the memory array. The blocks of 1's are evaluated based on a weighting assigned to positions within the...

20060136542 - Division algorithm: According to an aspect of the present invention, a quotient of a dividend divided by a divisor may be determined after reducing the dividend, divisor, and the remainder by using operations such as add, subtract, multiply, shift, AND which may result in reduced processor cycles (time)....

20060136543 - Data processing apparatus and method for performing floating point addition: A data processing apparatus and method are provided for adding n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises determination logic operable to determine the larger operand of the first and second operands, and alignment logic operable to align the...

20060129619 - Thinning filter and test apparatus: There is provided a thinning filter including a first thinning section for down-sampling input data, a first filter section for filtering the data down-sampled by the first thinning section to output the filtered data, and a second thinning section for further down-sampling the data filtered by the first filter section,...

20060129621 - Apparatus of selectively performing fast hadamard transform and fast fourier transform, and cck modulation and demodulation apparatus using the same: A Fast Fourier Transform (FFT) apparatus for selectively performing Fast Hadamard transform (FHT), and a complementary code keying (CCK) modulation/demodulation apparatus using the same are disclosed. In the present invention, OFDM module and CCK module are integrated as one module having lower complexity compared to conventional scheme by embodying the...

20060129620 - Fft apparatus for high data rate and method thereof: An FFT apparatus for quickly processing input signals and method thereof is disclosed. In performing the FFT for processing N input signals, four N/4-point FFT units implemented by radix-2 single-path delay feedback (R2SDF) units performs the FFT with respect to the input signals, and a radix-4 computation unit performs a...

20060129622 - Method and system for fast implementation of an approximation of a discrete cosine transform: A processor includes a multi-stage pipeline having a plurality of stages. Each stage is capable of receiving input values and providing output values. Each stage performs one of a plurality of data transformations using the input values to produce the output values. The data transformations collectively approximate at least one...

20060129623 - Division and square root arithmetic unit: A division and square root arithmetic unit carries out a division operation of a higher radix and a square root extraction operation of a lower radix. A certain bit number (determined on the basis of a radix of an operation) of data selected from upper bits of the output of...

20060129625 - low latency integer divider and integration with floating point divider and method: A method and device divides a dividend by a divisor, the dividend and the divisor both being integers. The method and device determine a maximum possible number of quotient digits (NDQ) based on a number of significant digits of the divisor and the dividend, normalizes the dividend and divisor, and...

20060129624 - Method and apparatus for performing a divide instruction: An apparatus and method to perform a division algorithm on an integer divisor and integer dividend. More particularly, embodiments of the invention relate to a technique to align integer operands such that a relatively fast division algorithm may be performed on the integer operands....

20060117077 - Method for identifying a subset of components of a system: A method of identifying a subset of components of a system based on data obtained from the system using at least one training sample from the system, the method comprising the steps of: obtaining a linear combination of components of the system and weightings of the linear combination of components,...

20060117078 - Performance optimized approach for efficient numerical computations: In particular, the present invention relates to a method and system for improving the efficiency of computational processes and specifically multiply and accumulate (“MAC”) processes such as the DCT (“Discrete Cosine Transform”) and/or IDCT (“Inverse Discrete Cosine Transform”) using a performance optimized method and associated hardware apparatus....

20060117079 - Galois field computation: A method and device for computing the multiplicative inverse of element x in Galois field GF(p2m) is proposed. In particular, when p is a prime number and m is an integer, the inverse may be constructed based on the observation that xpm+1 is en element in sub-field GF(pm) and the...

20060117080 - Data processing apparatus and method for performing floating point multiplication: A data processing apparatus and method are provided for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises multiplier logic operable to multiply the first and second n-bit significands to produce a pair of 2n-bit vectors....

20060117081 - Data processing apparatus and method for performing floating point multiplication: A data processing apparatus and method are provided for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises multiplier logic for multiplying the first and second n-bit significands to produce a pair of 2n-bit vectors, and...

20060117082 - Data processing apparatus and method for performing floating point multiplication: A data processing apparatus and method are provided for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result. Multiplier logic is used to multiply the first and second n-bit significands to produce a pair of 2n-bit vectors, and half adder logic...

20060117083 - Apparatus for solving differential equations: An apparatus for solving time-continuous differential equations is disclosed. The apparatus includes a group of hybrid integrators interconnected to each other. Each one of the hybrid integrators includes an analog integrator, a conversion logic and multiple digital registers. The analog integrator generates an analog output, and the conversion logic along...