Electrical computers: arithmetic processing and calculating inventions 05/06

20060112156 - Device for determining the rank of a sample, an apparatus for determining the rank of a plurality of samples, and the ith rank ordered filter: A rank-determining device determines the rank of a particular sample value from a set of digital sample values by utilizing two different thresholders that are implemented by comparators. The rank of the sample value is decomposed by thresholding the sample value with all of the sample values in the set...

20060112157 - Systolic de-multiplexed finite impulse response filter array architecture for linear and non-linear implementations: Described is a finite impulse filter response (FIR) filter for use by signal processors. A demultiplexer receives input data samples at an input data rate. The FIR filter includes a plurality of computational units arranged in a systolic array of taps and phases. Each computational unit operates at an array...

20060112158 - Method of estimating a total path delay in an integrated circuit design with stochastically weighted conservatism: A method and computer program product for estimating total path delay in an integrated circuit design includes steps of: (a) receiving as input a number of stage delays and stage delay variations constituting a path in an integrated circuit design; (b) calculating a sum of the stage delays; (c) calculating...

20060112159 - Processor: The present invention provides a processor including data manipulating means for generating an arbitrary combination of elements of a first input vector and elements of a second input vector, arithmetic means for performing a product-sum operation on the combination, and repetition control means for controlling the generation of the combination...

20060112160 - Floating-point number arithmetic circuit: Disclosed herein is a floating-point number arithmetic circuit for efficiently supplying data to be performed arithmetic operation. The floating-point number arithmetic circuit includes an floating-point number arithmetic unit for performing a predetermined floating-point number arithmetic operation on a floating-point number of a predetermined precision, and a converting circuit for converting...

20060106904 - Apparatus and methods for implementation of mathematical functions: Apparatus and methods for implementation of mathematical functions apparatus providing both speed and accuracy. Disclosed are specific circuits and methods of operation thereof that may be used for the purpose of implementing an exponential function, a squaring function, and a cubic function, using the same basic circuit. By applying a...

20060106903 - Arithmetic unit of arbitrary precision, operation method for processing data of arbitrary precision and electronic equipment: An arithmetic unit of arbitrary-precision, including: a main processing unit, which splits up the first and the second arbitrary-precision values into N-bit (where N is a natural number) operands respectively in the-least-significant-bit-first order for computing with the arbitrary-precision data and consecutively outputting a series of pairs of the first and...

20060106901 - Device and method for robust decoding of arithmetic codes: The invention concerns a decoder (2) comprising a first input for receiving a coded flow of second binary elements (Yd). It comprises a second input for receiving channel properties (1c) designed to define probabilities of receiving second binary elements, upon transmitting first binary elements, a first module (12) defining a...

20060106902 - Efficient computation for eigenvalue decomposition and singular value decomposition of matrices: For eigenvalue decomposition, a first set of at least one variable is derived based on a first matrix being decomposed and using Coordinate Rotational Digital Computer (CORDIC) computation. A second set of at least one variable is derived based on the first matrix and using a look-up table. A second...

20060106905 - Method for reducing memory size in logarithmic number system arithmetic units: A method for performing addition/subtraction on logarithmic number system (LNS) operands x and y that uses a single lookup table. The lookup table is populated by values of ln(1+exp(−α)) where α is an absolute value of difference of x and y. To perform an addition operation, the lookup table is...

20060106906 - Digital filter system and method: A method is disclosed for providing a digital filter system for providing a low pass filter function to a digital input. The method includes the steps of determining a finite impulse response of the input, determining a transfer function of the finite impulse response and providing a polynomial, identifying a...

20060106907 - Method of analyzing correlations among four variables in two-dimension configuration and computer accessible medium: A method of analyzing a correlation among four variables in a two dimensions configuration and a computer accessible medium for storing a program thereof are provided. The method comprises providing a plurality of data comprising a first variable, a second variable, a third variable and a fourth variable. The first...

20060106908 - Low complexity bit-parallel systolic architecture for computing c+ab, ab, c+ab2 or ab2 over a class of gf (2m): A systolic architecture for computing C+AB, AB, C+AB2 or AB over a class of GF(2m) free global connection, wherein the A, B and C are the input elements of the GF(2m). The systolic architecture includes an inner product unit and a modular unit. The inner product unit includes m2 pieces...

20060106909 - System and method for mapping mathematical finite floating-point numbers: A floating-point number is encoded into a binary string. A left-to-right comparison of the binary string determines relative magnitude of the floating-point number. If the floating-point number is negative, then take an absolute value of the floating-point number. The resulting binary string conversion is then complemented. If the floating-point number...

20060106910 - Galois field polynomial multiplication: In one aspect, a multiplier for performing multiplication of a first operand and a second operand is provided. The multiplier comprises a matrix having a plurality of matrix elements arranged in a plurality of columns, a first plurality of storage elements to store at least a portion of the first...

20060101103 - Representing implicit curves of procedural geometric surfaces: Compact and accurate piecewise parametric representations of implicit curves may be achieved by iteratively selecting ranges of parameterizing regions and testing each for satisfying an intervalized super convergence test. In one aspect, the implicit curves is represented as a compact form of one or more representations of such convergence regions....

20060101104 - Optimizing layout of an application on a massively parallel supercomputer: A general computer-implement method and apparatus to optimize problem layout on a massively parallel supercomputer is described. The method takes as input the communication matrix of an arbitrary problem in the form of an array whose entries C(i, j) are the amount to data communicated from domain i to domain...

20060101105 - Double shift mechanism and methods thereof: In a processor, a concatenation of contents of two registers having a fixed number of one-bit data storage elements are shifted by a software-defined, controllable amount and the fixed number of bits are selected from the shifted concatenation as output....

20060101106 - Methods and apparatus for computing the input and output signals of a linear shift-variant system: This invention is based on a new signal processing transform named Rao Transform (RT) which was invented recently by the author of the present invention. Forward RT provides a computationally efficient method and an associated apparatus for computing the output signal of a Linear Shift-Variant System (LSVS) from the input...

20060101107 - Apparatus for controlling rounding modes in single instruction multiple data (simd) floating-point units: An apparatus for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating...

20060101108 - Using a leading-sign anticipator circuit for detecting sticky-bit information: A method, an apparatus, and a computer program are provided to more efficiently generate a sticky bit in a Floating Point Design. Traditionally, separate ORing logic or OR trees were employed to compress the stick outputs of a normalization shifter into at least one sticky bit. However, this design has...

20060095486 - Generation of rtl to carry out parallel arithmetic operations: Computer-implemented method and system for generating an optimized description of an arithmetic function comprising at least two of an addition, a multiplication, and a rounding operation to be carried out on a plurality of data bits in a plurality of registers of an electronic circuit, the method comprising the steps:...

20060095484 - Method and system for solving an optimization problem: This invention provides a method and system for solving an optimization problem under a set of constraints. A set of solutions is evaluated under the set of constraints. Initial violation metrics and states are generated, based on at least one constraint corresponding to the solutions violating the constraints. A set...

20060095485 - System and method for permuting a vector: In one embodiment, a method of permuting a vector comprises providing vector entries of the vector to an input stage of a permuting structure, wherein the permuting structure comprises a plurality of stages and interconnections for groups of vector entries between the plurality of plurality of stages such that any...

20060095487 - Binary representation of number based on processor word size: A method of converting a number to a binary representation based on a processor word size is described. In accordance with the method, a predetermined size segment of a number is converted to a binary representation wherein the predetermined size segment is based on the processor word size. Also described...

20060095488 - Method and system for estimating and applying a step size value for lms echo cancellers: Disclosed is an improved method and apparatus for estimating and applying a step size value for a least mean squares echo canceller. A power estimate of an excitation signal is compared to a reference power level to determine a shift adjustment. The shift adjustment is added to a reference shift...

20060095491 - Digital-signal processing apparatus, digital-signal processing method, program, and authentication apparatus: A digital-signal processing apparatus in which the efficiency of processing data can be prevented uniformly. The apparatus includes: an extracting unit that extracts a part of real data input; a selecting unit that selects a data size from similar data sizes falling in a range, in accordance with the size...

20060095490 - Method for representing complex numbers in a communication system: A method for storage for complex numbers that employs a shared exponent field is disclosed. Rather than each floating point component of an complex number having its own distinct signed mantissa and exponent fields, each component includes a distinct signed mantissa field and shares an exponent field, thereby increasing the...

20060095489 - Representation of implicit curves for procedural surfaces: Compact and accurate piecewise parametric representations of implicit functions may be achieved by iteratively selecting ranges of parameterizing regions and testing each for satisfying an intervalized super convergence test. In one aspect, the implicit function is represented as a compact form of one or more representations of such convergence regions....

20060095492 - System and method for a fast fourier transform architecture in a multicarrier transceiver: A Fourier transform architecture and system for FFT and IFFT processing within multicarrier transceiver is disclosed that includes a programmable butterfly component, a memory and a programmable address generation unit. The architecture includes a butterfly component configured to perform a plurality of radix butterfly calculations, and a four bank memory...

20060095493 - Equivalent material constant calculation system, storage medium storing an equivalent material constant calculation program, equivalent material constant calculation method, design system, and structure manufacturing method: An equivalent material constant calculation system that calculates an equivalent material constant of a structure constituted by a plurality of materials includes a shape data input portion that inputs shape data, a material data input portion that inputs material constant data, a dividing portion that divides the structure into a...

20060095494 - Method and apparatus for efficient software-based integer division: A method and apparatus to perform efficient software-based integer division. The equivalent of a hardware-based integer division operation is enabled via a reciprocal multiplication operation that is facilitated by a minimum combination of multiplication (and/or add) and shift operations. Properties and equations are derived for determining minimum multiplication and shift...

20060095495 - Apparatus for hybrid multiplier in gf(2m) and method thereof: An apparatus and method for hybrid multiplication in GF(2m) by which trade-off between the area and the operation speed of an apparatus for a hybrid multiplier in finite field GF(2m) can be achieved are provided. The apparatus for hybrid multiplication includes: a matrix Z generation unit generating [m×k] matrix Z...

20060095496 - Power of two multiplication engine: A multiplication engine is described in which a decision threshold engine utilizes a Y-adder powers of two shift table to iteratively generate shift-add combinations. The shift-add combinations are output in a sequence with decreasing levels of contribution wherein the accuracy of the associated multiplication increases up to any desired level...