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Electrical computers: arithmetic processing and calculating inventions 04/06

Recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing format for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.

   04/27/2006 > 7 patent applications in 5 patent subcategories.

20060089956 - Classification unit and methods thereof: A classification unit is to process an odd number of inputs in a single instruction cycle by comparing all distinct pairs of inputs and selecting one of the inputs based on the comparisons....

20060089955 - Two's complement circuit: A operator is located between two converters that convert data between floating-point format and a predetermined format. The operator operates on predetermined format data, which consists of the same sign bit, the same exponent, and the two's complement of the mantissa of the corresponding floating-point data. When the operator is...

20060089957 - Adaptive equalizer and method for the same: An equalizer may include, filter an input data signal based on a plurality of filtering coefficients, and outputs an output data signal, determine whether filtering coefficients satisfy a condition in response to a bit selection signal, and output the filtering control signals based on the determination result, and generate the...

20060089958 - Periodic signal enhancement system: A signal enhancement system improves the understandability of speech or other audio signals. The system reinforces selected parts of the signal, may attenuate selected parts of the signal, and may increase SNR. The system includes delay logic, an adaptive filter, and signal reinforcement logic. The adaptive filter may track one...

20060089959 - Periodic signal enhancement system: A signal enhancement system improves the understandability of speech or other audio signals. The system reinforces selected parts of the signal, may attenuate selected parts of the signal, and may increase SNR. The system includes delay logic, a partitioned adaptive filter, and signal reinforcement logic. The partitioned adaptive filter may...

20060089960 - Reducing errors in performance sensitive transformations: The invention provides a method, data compression system, apparatus, and article of manufacture which reduce the error in transform equations in which constants are replaced by approximations. According to the invention transform constants are replaced with approximations which are a function of an integer and a floating point value. The...

20060089961 - Mixed-type adder comprising multiple sub-adders having different carry propagation schemes: Disclosed is a mixed-type adder with optimized design costs. The mixed-type adder includes I sub adders, (where, I is a positive number larger than 1). An overall bit width of the mixed-type adder is divided into I bit groups which are respectively allocated to the I sub adders. The I...

  
04/20/2006 > 3 patent applications in 3 patent subcategories.

20060085495 - Wireless input device: A wireless input device for controlling and inputting data to an electronic apparatus is provided. The wireless input device includes a housing, a first input unit, and a second input unit. The first and second input units are respectively on opposite sides of the housing, thereby connecting to the housing....

20060085496 - Programmably configurable digital filter: A digital filter includes a plurality of connected component digital filters. Control signal generation circuitry is configured to receive a tap output signal from each of at least some of the component digital filters and to process the received tap output signals to generate a control signal to output from...

20060085497 - Matrix-valued methods and apparatus for signal processing: The present invention relates to a novel matrix-valued transform framework to process digital signals. According to one aspect of the invention, matrix-valued methods and apparatus are described to transform a vector-valued discrete-time data sequence from time-domain into frequency-domain. In another aspect, matrix-valued methods and apparatus are described to transform a...

  
04/13/2006 > 6 patent applications in 4 patent subcategories.

20060080373 - Compensating for errors in performance sensitive transformations: The invention provides a method, a data analyzing system, an apparatus, and article of manufacture which reduce the error in transform equations in which constants are replaced by approximations. This is achieved by factoring an adjustment factor into the calculations which serves to reduce the error introduced by the approximations....

20060080374 - Processing of performance sensitive transforms: The present invention provides a method, apparatus, and article of manufacture for controlling truncation error which is introduced when performing a transform equation as a result of lowering the precision of elements of the equation using shift right operations. This is achieved by associating a predetermined truncation amount with a...

20060080375 - Method and apparatus for inverse discrete cosine transform implementation: A data processing apparatus and the same method utilize a first and a second IDCT circuits, a transpose memory, and a controller to perform a first and a second 1-D IDCT procedures. The apparatus performs IDCT procedure on a plurality of incoming data with zero and/or non-zero information. The apparatus...

20060080376 - Galois field multiplication system and method: A present invention Galois field multiplier system and method utilize lookup tables to generate one partial product term and one feedback term in one clock cycle. In one embodiment, a Galois field multiplier system includes a plurality of shift registers, a plurality of exclusive OR components, a partial product lookup...

20060080377 - Galois field multiplier and multiplication method thereof: A Galois field multiplier is provided. The Galois field multiplier comprises a lookup table device and an operation circuit. Wherein, the lookup table device obtains a coefficient matrix W by looking up a multiplicator coefficient table based on a multiplicator S. The operation circuit is coupled to the lookup table...

20060080378 - Parallel operations on multiple signed elements in a register: The present invention provides methods, apparatus, and article of manufacture for performing parallel operations on multiple signed elements which have been packed into a binary value, each element being associated with a different set of bits. A signs binary value is obtained which contains the sign bits for each element...

  
04/06/2006 > 5 patent applications in 3 patent subcategories.

20060075008 - Calculator device having a usb connection: A method for transferring a signal between a calculator device having a USB connector and a remote device is described. The method includes: connecting the calculator device with the remote device using the USB connector; transmitting a signal from the remote device to the calculator device using the USB connector;...

20060075009 - Method of diagnosing an operations system: A method of diagnosing a distributed operational system having a field device, a field processing module coupled to the field device, a bitbus, a fieldbus, and an auxiliary processing module communicating with the bitbus and the fieldbus. The method includes generating a field operating characteristic at the field device, processing...

20060075010 - Fast fourier transform method and apparatus: A method and apparatus, especially suited for computers that can execute fused multiply-add instructions, for performing a fast Fourier transform (FFT) are disclosed. Divisions by zero that create a risk of error in other methods are avoided. In a first example embodiment, a zero divisor is detected and the division...

20060075012 - Efficient implementation of dsp functions in a field programmable gate array: An efficient implementation of DSP functions in a field programmable gate array (FPGA) using one or more computational blocks, each block having of a multiplier, an accumulator, and multiplexers. The structure implements most common DSP equations in a fast and a highly compact manner. A novel method for cascading these...

20060075011 - System and method for optimizing polynomial expressions in a processing environment: A method for optimizing polynomial expressions is provided that includes generating kernels in order to form a kernel and co-kernel matrix and generating a cube literal matrix, which includes a plurality of cubes. Rectangles are identified on the kernel and co-kernel matrix and the rectangles are used to find common...

Previous industry: Data processing: database and file management or data structures
Next industry: Electrical computers and digital processing systems: multicomputer data transferring or plural processor synchronization


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