Electrical computers: arithmetic processing and calculating inventions 03/06

20060069705 - Arithmetic processing device: An arithmetic processing device comprises a menu displaying unit which displays a menu screen for a plurality of arithmetic processings when the predetermined key is operated, each arithmetic processings being allocated to each numeric keys; an arithmetic processing unit which, when a numeric key allocated to any one of the...

20060069706 - Random number generator and method for generating random numbers: The invention relates to a method for generating random numbers in which oscillating digital output signals (A1, A2, . . . , AL) of unequal or equal periodicity are generated by at least two ring oscillators (32, 33, 34), an external parity signal (PS) representing a logical state (“0,” “1”)...

20060069707 - System and method for introducing dither for reducing spurs in digital-to-time converter direct digital synthesis: A direct digital synthesizer (DDS) (300) that uses a system for reducing spurious emissions in a digital-to-time converter (DTC) (317). The DDS (300) includes one or more dither sources (307) and a random access memory (RAM) (305). The RAM (305) utilizes a look-up table for storing delay error values by...

20060069708 - Broad-dynamic filtering procedure for a recursive digital filter installed in a signal processor (dsp) operating with integers: The present invention relates to a filtering procedure for recursive digital filters installed in signal processors (DSP) operating with integers. It comprises two calculation procedures coupled with the classical calculation procedure of a recursive filter, the first of which, when calculating the output value of the sample, takes into account...

20060069709 - K-means clustering using t-test computation: A method, apparatus, and system are provided for k-means clustering using t-test computation. According to one embodiment, k-means clustering is performed on a dataset. In performing k-means clustering, the dataset having various points is partitioned into several clusters. The closeness of a given point to a given cluster is determined....

20060069710 - Montgomery multiplier for rsa security module: The present invention discloses a Montgomery multiplier for an RSA security module secured from a differential power analysis attack. The Montgomery multiplier includes the first filtering means for receiving the first input signal and the second input signal represented by an asynchronous double line method, and selectively outputting the second...

20060059213 - Dedicated encrypted virtual channel in a multi-channel serial communications interface: A data processing system, circuit arrangement, and method to communicate data over a multi-channel serial communications interface (14) using a dedicated encrypted virtual channel from among multiple virtual channels supported by the communications interface (14). Encryption for the dedicated encrypted virtual channel is provided by a hardware encryption circuit (34)...

20060059214 - Systems and methods for automated equation buildup: Systems and methods for automatically building up an equation entered into a computer system can include an input module that accepts input of the equation in a linear string format, and an interpret module that interprets the input and automatically determines when a buildup point is reached. Systems can further...

20060059215 - Cordic unit: A CORDIC unit for the iterative approximation of a vector rotation through a rotary angle θ by a number of elementary rotations through elementary angles αi, including elementary rotation stages for respectively effecting an elementary rotation through an elementary angle αi as an iteration step in the iterative approximation. After...

20060059217 - Mathematical expression buildup and builddown: Systems and methods for manipulating mathematical expressions in a computer system. A system can include a builddown module programmed to builddown a mathematical expression from a two-dimensional format to a linear format, the builddown module being programmed to associate a special property of the two-dimensional format of the mathematical expression...

20060059216 - Method for square root computation: The present invention describes a method for square root computation, in which a shift-comparison operation is introduced into the computation process so as to obtain correction factors and adjusting factors. The bits of the correction factors are shifted to form estimation terms, and then the adjusting factors are used to...

20060059218 - System and method for video processing: Method and apparatus for decimating or sub-sampling image data which uses fixed delay intervals to accumulate a weighted sum of input samples. The accumulated sum is output at selected intervals, the interval determining the degree of decimation. The apparatus can take the form of a Finite Impulse Response (FIR) decimation...

20060059219 - Method and apparatus for performing modular exponentiations: An arrangement is provided for performing modular exponentiations. A modular exponentiation may be performed by using multiple Montgomery multiplications. A Montgomery multiplication comprises a plurality of iterations of basic operations (e.g., carry-save additions), and is performed by a Montgomery multiplication engine (MME). Multiple MMEs of smaller sizes may be chained...

20060059220 - Method and apparatus for performing montgomery multiplications: An arrangement is provided for performing Montgomery multiplications. A Montgomery multiplication comprises a plurality of iterations of basic operations (e.g., carry-save additions), and is performed by a Montgomery multiplication engine (MME). Basic operations in each iteration may be performed by multiple Montgomery multiplication processing elements (MMPEs). An MME may be...

20060059221 - Multiply instructions for modular exponentiation: A method and apparatus for increasing performance of a multiplication operation in a processor. The processor's instruction set includes multiply instructions that can be used to accelerate modular exponentiation. Prior to issuing a sequence of multiply instructions for the multiplication operation, a multiplier register in a multiply unit in the...

20060059222 - Logic entity with two outputs for efficient adder and other macro implementations: An improved logic entity with two outputs for efficient adder and other macro implementations providing fast response with reduced area requirements, comprising a first lookup table for generating a first output for the carry out value for a carry-in of zero and a second output for the sum value for...

20060053187 - Digital filter for transmission-end pulse shaping: The digital filter has a finite impulse response, whose length corresponds at most to the duration of N input values, with the filter emitting an output signal which is n-times oversampled in comparison to the input signal (I, Q). In this case, a means (38.1-38.5) for storage of a plurality...

20060053186 - Methods and systems for efficient filtering of digital signals: A method in a signal processor for filtering samples in a digital signal is provided. An approximate filtered sample is generated as a function of eight samples of the digital signal. A correction is generated as a function of the eight samples, and a filtered sample is generated by modifying...

20060053185 - Reflection filter: A method and apparatus for generating a reflection filter. The method comprises the steps of determining an averaged step response of an acquired signal and generating a spectrum response from the averaged step response. A time at which a reflection in the averaged step response begins is determined and information...

20060053188 - Apparatus with redundant circuitry and method therefor: An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for...

20060053189 - Graphics processing logic with variable arithmetic logic unit control and method therefor: Briefly, graphics data processing logic includes a plurality of parallel arithmetic logic units (ALUs), such as floating point processors or any other suitable logic, that operate as a vector processor on at least one of pixel data and vertex data (or both) and a programmable storage element that contains data...

20060053190 - Construction of a folded leading zero anticipator: An apparatus, a method, and a computer program are provided for anticipating leading zeros for a Floating Point (FP) computation. Traditional leading zero anticipators (LZA) are typically very wide. To reduce the width of the LZA, it is subdivided to two smaller LZA that compute edge vectors for the most...

20060053191 - Floating point encoding systems and methods: Systems and methods for encoding floating point numbers. A system can include encoding logic which encodes invalid floating point representations as valid data. Decoding logic can be used to recognize the invalid floating point representations and map can provide the invalid floating point representations to valid data values. The decoding...

20060053192 - Apparatus and method for implementing efficient arithmetic circuits in programmable logic devices: Efficient implementation of arithmetic circuits in programmable logic devices by using Look-Up Tables (LUTs) to store pre-calculated values. A table look-up operation is performed in place of complex arithmetic operations. In this way, at the expense of a few LUTs, many logic elements can be saved. This approach is particularly...

20060053193 - Complex multiple feedback filter: A complex filter includes an I channel having a first I channel output and a second I channel output and a Q channel having a first Q channel output and a second Q channel output. The second I channel output is input to the Q channel through a first passive...

20060047734 - Fast conversion of integer to float using table lookup: Method, system and computer program product for converting integers to floating point values in a data processing system. The method utilizes data flow analysis and control flow analysis to recognize that a particular integer that is to be converted contains only a limited range of values. Knowledge of this limited...

20060047733 - Method for representing integer and floating point numbers in a binary orderable format: A method is described for converting standard integer and floating point formatted numbers to an improved integer and floating point numbers which are binary orderable. Standard integers are represented in two's complement format, to make standard integers binary orderable, the sign bit is flipped. To make floating point numbers binary...

20060047735 - Random number generator: A pseudo-random number generator employs a value in an existing sequence of numbers as an index into a table of irrational numbers. The value that is retrieved from the table is used to derive another value that is combined with multiple other values in the sequence to generate the next...

20060047736 - Arithmetic circuitry for averaging and methods thereof: A functional unit includes one or more instances of arithmetic circuitry for calculating averages. Each instance of arithmetic circuitry includes first, second and third adders, each having first and second inputs and an output that is a sum of the first and second inputs and a carry-in bit. An output...

20060047737 - Simulation of processes, devices and circuits by a modified newton method: f

20060047738 - Decimal rounding mode which preserves data information for further rounding to less precision: A method of processing data employs a new rounding mode called “round for reround” on the original arithmetic instruction in the hardware precision, and then 2) invoking an instruction which specifies a variable rounding precision and possibly explicitly sets the rounding mode which we have called the ReRound instruction. The...

20060047739 - Decimal floating-point adder: A decimal floating-point adder is described that performs addition and subtraction on decimal floating-point operands. The decimal floating-point adder includes an alignment unit that receives a first floating-point number and a second floating-point number, and aligns significands associated with the floating-point numbers such that exponents associated with the floating-point numbers...

20060047740 - Decimal computing apparatus, electronic device connectable decimal computing apparatus, arithmetic operation apparatus, arithmetic operation control apparatus, and program-recorded recording medium: Decimal calculation apparatus, which performs multidigit decimal calculation with the number of calculation digits set in calculation instruction, comprises multidigit memory section capable of storing values with greater numbers of digits than the number of digits of a predetermined digit unit in plurality of memory areas; calculation-instruction memory section which...