Electrical computers: arithmetic processing and calculating inventions 02/06

20060041609 - System and method for multi-dimensional lookup table interpolation: A technique for using a one or two dimensional table lookup to provide the appropriate index and fraction for a second lookup table. The second lookup table can be a multi-dimensional lookup table. The one or two dimensional lookup table allows nonlinear conversion between input values and output values obtained...

20060041610 - Processor having parallel vector multiply and reduce operations with sequential semantics: A processor comprises a plurality of arithmetic units, an accumulator unit, and a reduction unit coupled between the plurality of arithmetic units and the accumulator unit. The reduction unit receives products of vector elements from the arithmetic units and a first accumulator value from the accumulator unit, and processes the...

20060036664 - Efficient fir filter suitable for use with high order modulation radio frequency transmitters: A linear filter includes an input node to receive an X-bit digital representation of a signal to be filtered; an output node to output a B-bit digital representation of a filtered output signal; an N-bit delay line having an input coupled to the input node and N outputs; and a...

20060036665 - Data processing circuit: The invention relates to a data processing system for performing a polyphase filtering. This circuit comprises functional units (304, 305, 306) able to perform polyphase filterings, and a memory device (301, 302, 308) for storing data and coefficients. The functional units receive in parallel data and coefficients coming from the...

20060036666 - Method, circuit, codec and computer program product for performing a modified discrete cosine transform: The invention relates to performing an MDCT of a digital input signal of length N, wherein by generating a specific intermediate signal of length N/2 the MDCT can be performed by a number of only N2/4 multiplications of data values of the intermediate signal with cosine values....

20060036667 - Methods and apparatus for an efficient floating point alu: The present invention provides an improved technique for performing a near processing path exponent difference in an arithmetic logic unit (ALU) of a microprocessor. In one embodiment, an apparatus having a separate logic circuit for near processing path and far processing path subtraction generates exponent difference signals using only two...

20060036668 - High speed multiplier: A current summing FIR filter can be implemented with multiple differential input stages and variable tail currents. The variable tail currents can be used to appropriately weight the present and previous digital input signals. The weighted outputs of the differential transistor pairs can be summed to provide a filtered output...

20060031271 - Methods and apparatus for predicting an underflow condition associated with a floating-point multiply-add operation: Methods and apparatus for predicting an underflow condition associated with a floating-point multiply-add operation are disclosed. An example apparatus obtains a first operand value and a second operand value. The example apparatus then determines if the second operand value subtracted from the first operand value is greater than a minimum...

20060031272 - Alignment shifter supporting multiple precisions: An apparatus, a method, and a computer program are provided for fully utilizing a double precision Floating Point (FP) alignment shifter. In conventional FP adders, and other FP computational units, double precision FP alignment shifters are utilized to perform both double and single precision alignment shifts. However, when a conventional...

20060031273 - Tunable multi-phase-offset direct digital synthesizer: A plasma control system including a direct digital synthesizer (DDS) for generating more than one individual RF power signal, where the individual RF power signals are combined to define a combined RF power signal. The DDS includes an accumulator which receives a phase increment signal that defines a frequency of...

20060031275 - Digital if processing block having finite impulse response (fir) decimation stages: A digital IF processing block including a decimation filter having FIR decimation stages provides improved performance over a Hogenauer decimating filter. The filter comprises multiple integrator stages followed by multiple FIR decimating stages. The zeros of the filter are tunable by adjusting the integer coefficients of the FIR stages providing...

20060031274 - Parallel filter realization for wideband programmable digital radios: A block polyphase filter is constructed of a set of filter blocks having different filter functions, and being arranged for parallel processing of portions of an input sequence of signals. Signals of the input sequence are divided among the blocks by a demultiplexer for processing at a clock frequency lower...

20060031276 - Signal-processing apparatus and method: First and second coefficients are fed into a Fast Fourier Transform unit through real number input and imaginary number input portions thereof, respectively, to perform the Fast Fourier Transform of the entered first and second coefficients, thereby producing a frequency-domain coefficient vector. The Fast Fourier Transform of an input signal...

20060031277 - Fft and fht engine: A transformation engine includes an address generator; a butterfly unit coupled to the address generator; a twiddle LUT coupled to the address generator; and a multiplier having a first input coupled to the butterfly unit and a second input coupled to the twiddle LUT....

20060031279 - Highly parallel structure for fast multi cycle binary and decimal adder unit: An adder circuit for adding two binary or two decimal operands A and B in which the carries are calculated directly from the input operands A and B without including the plus 6 or minus 6 operations into the carry calculation. For all timing critical functions the reduced input data...

20060031278 - Multi-value digital calculating circuits, including multipliers: Apparatus and method for performing multi-value arithmetic operations are disclosed. Multi-value signals can be added, subtracted and multiplied using a first truth table to generate a residue and a second truth table to generate a carry. Additionally, method and apparatus to efficiently perform the function a0b1+a1b0 on multi-value signals are...

20060031280 - Carry-skip adder having merged carry-skip cells with sum cells: A multi-bit adder includes a carry chain, a carry-skip network, sum cells, and a carry-sum cell. The carry chain propagates, generates, or kills carry-in bits. The carry-skip network is coupled to the carry chain to selectively skip the carry-in bits over at least one portion of the carry chain. The...

20060026223 - Apparatus and method for reducing the latency of sum-addressed shifters: The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group...

20060026224 - Method and circuit for combined multiplication and division: Previously known analog transistor circuits that compute the “outer product” of two probability mass functions are extended to compute also divisions. Such circuits can be used in hardware implementations of certain algorithms including “generalized belief propagation”, which have applications in many inference problems including the decoding of error correcting codes....