Electrical computers: arithmetic processing and calculating inventions 12/05

20050289201 - Method for determining filter coefficients of a digital filter and digital filter: In a method for determining filter coefficients of a digital filter, particularly in UMTS, the predetermined filter co-efficients by are divided by a same scaling factor s and then quantized in that counted from the most significant bit onwards only a certain number n of “1” bits is used and...

20050289202 - Integrated calendar: This document discloses a system and method that assists in collecting, integrating, and displaying calendar data from a plurality of data source applications includes several components. In one implementation, a first client connector communicates with a first client application. A plurality of data source connectors communicate with a plurality of...

20050289203 - Efficient execution and emulation of bit scan operations: Methods are disclosed to implement bit scan operations using properties of two's complement arithmetic and compute zero index instructions. A data value may be provided and the most-significant or least-significant bit may be determined using the methods set forth herein....

20050289206 - Digital filter design method and device, digital filter design program, digital filter: A numerical string consisting of a ratio of “−1, m, −1” or “1, m, 1” is subjected to a predetermined moving average calculation n times. A numerical string thus obtained is used as filter coefficients of a basic filter and at least one basic filter is combined in an arbitrary...

20050289205 - Methods and systems for efficient filtering of digital signals: A method in a signal processor for filtering samples in a digital signal is provided. An approximate filtered sample is generated as a function of four samples of the digital signal. A correction is generated as a function of the four samples, and a filtered sample is generated by modifying...

20050289204 - Parallel feedback processing: Embodiments of a parallel feedback processor are disclosed. The parallel feedback processor includes a plurality of parallel coupled feedback filters. Each feedback filter includes a non-linear operator. At least one of feedback filter includes a plurality of sub-filters. Each sub-filter computes a one of possible non-linear operator filter outputs of...

20050289207 - Fast fourier transform processor, dynamic scaling method and fast fourier transform with radix-8 algorithm: The present invention provides a fast Fourier transform processor, dynamic scaling method and fast Fourier transform with radix-8 algorithm. It reduces quantization errors generated from the operation by using a matrix prefetch buffer-based fast Fourier transform processor. Operation sizes of the matrix prefetch buffer as block sizes the invention adjust...

20050289208 - Methods and apparatus for determining quotients: Methods, apparatus, and articles of manufacture for determining quotient values are disclosed. An example method identifies a reciprocal value of a divisor value. A bias value is then identified and a biased quotient value is determined based on a dividend value, the reciprocal value, and at least a portion of...

20050289209 - Method and system of achieving integer division by invariant divisor using n-bit multiply-add operation: An integer division system for a dividend and a divisor includes a pre-calculation module to select a reciprocal approximation and a rounding error compensation value of the divisor, and an instruction generation module to generate at least an instruction to calculate a quotient of the dividend using the reciprocal and...

20050289210 - Recursive carry-select topology in incrementer designs: A recursive carry-select substitution operation is used to optimize the design of an incrementer and similar logic devices. A carry look-ahead incrementer features XOR gates in which the XOR gates in one or more MSBs of the incrementer can be pushed back by substituting an equivalent carry-select circuit, the carry-select...

20050289211 - One bit full adder with sum and carry outputs capable of independent functionalities: A one bit full adder with sum and carry outputs performs independent functions. The full adder includes at least one look up table (LUT) for implementing a sum function, and at least one carry circuit for implementing a carry/borrow function. The carry circuit includes a first multiplexer having first and...

20050283506 - Attenuator, data signal processor, method for acquiring attenuation of attenuator, recording medium, and computer data signal: An address generator is supplied with a designated gain GT, and generates exponent data n and an address of mantissa A. The address of mantissa A is set based on an accuracy of the designated gain GT. A mantissa-coefficient acquiring unit is so structured as to acquire a mantissa-coefficient k...

20050283505 - Distribution goodness-of-fit test device, consumable goods supply timing judgment device, image forming device, distribution goodness-of-fit test method and distribution goodness-of-fit test program: A distribution goodness-of-fit test device for testing whether measured data matches an estimated probability distribution has a counting section determination unit, a counting unit and a goodness-of-fit test unit. The counting section determination unit determines according to the number of the measured data, widths of counting sections for counting the...

20050283507 - Selective sequence generation method and apparatus: A sequence generator is configured to be re-initialized to a value selected derived from a candidate group that is derived from a predetermined value. If and when the re-initializing is performed, it is fully performed within about one clock cycle of setting the sequence generator to the predetermined value. The...

20050283510 - Digital filter using memory to emulate variable shift register: A digital filter uses memory to emulate a variable shift register. Data samples are stored in a memory. The data samples are read from the memory, multiplied with corresponding coefficients stored in the same or a different memory, logically shifted, and written back into the memory so as to emulate...

20050283508 - Micro-programmable digital filter: A micro-programmable digital filter includes a plurality of programmable filter elements, an instruction memory for storing a control program, at least one instruction decoder for programming the filter elements based on the control program, and arithmetic logic for selectively scaling and accumulating output values received from the filter elements and...

20050283509 - Micro-programmable filter engine: A micro-programmable filter (MFE) engine includes multiple programmable filter elements and a microcode controller. The filter elements can be configured, controlled, and combined in different ways to implement different types of filters. The MFE preferably supports multiple-execution instructions that allow a single instruction to perform multiple moves into accumulators for...

20050283511 - Cross-feature analysis: Disclosed is a method of automatically identifying anomalous situations during computerized system operations that records actions performed by the computerized system as features in a history file, automatically creates a model for each feature only from normal data in the history file, performs training by calculating anomaly scores of the...

20050283512 - Circuit and method for encoding data and data recorder: To provide a data encoding circuit capable of securing real-timeness of a recording operation even in a memory of a low operation clock frequency by reducing the number of times of accessing the memory, and simultaneously reducing power consumption and memory costs. Prior to error correction encoding of a PI...

20050283513 - Method of calculating intersections between triangle and line segment and program therefrom: A coordinate system R is set in which P0 is a coordinate origin, P0P1 conforms to a first U axis to have a unit length, P0P2 conforms to a second V axis to have a unit length, and P0P1×P0P2 is a unit vector conforming to a third N axis. A...

20050283514 - Method and apparatus for calculating a modular inverse: a third calculator operable to calculate a Montgomery modular product of the output of the first calculator and 22*k−z in the event that z≠k; a fourth calculator operable to calculate a Montgomery modular product of the output from the third calculator and the second input variable in the event that...

20050283515 - Methods of factoring and modular arithmetic: A method of factoring numbers in a non-binary computation scheme and more particularly, a method of factoring numbers utilizing a digital multistate phase change material. The method includes providing energy in an amount characteristic of the number to be factored to a phase change material programmed according to a potential...

20050283516 - Apparatus for evaluating a mathematical function: Please replace the Specification with the clean copy of the Specification enclosed herewith. No new matter is entered thereby. The enclosed substitute specification is identical to the original specification as filed, except that same incorporates the specification amendment made in the Amendment Before First Office Action dated May 27, 2005....

20050278399 - Apparatus and method for efficient generation of delta files for over-the-air upgrades in a wireless network: A method of generating a composite delta file based on the differences between an original file and an upgraded file. The method comprises the steps of: 1) segmenting the original binary file into segments of size N; 2) segmenting the upgraded binary file into segments of size N; 3) detecting...

20050278401 - Apparatus and method for motion vector search and post filtering with reduced hardware resources: An image processing circuit is composed of: a plurality of registers retaining pixel data, respectively; a plurality of absolute difference calculator/adders; at least one selective multiplier, each disposed between associated one of said registers and associated one of said absolute difference calculator/adders; and an adder calculating a sum of outputs...

20050278400 - Test data compression and decompression method using zero-detected run-length code in system-on-chip: A method of effectively compressing a test vector is introduced for testing a system-on-chip (SOC) semiconductor device. Since the number of test vectors is increased in a SOC, the number of ‘0’s is increased if adjacent test vectors are properly aligned using an ordering algorithm. ‘0000’ is considered as a...

20050278402 - Random number generating method and random number generating apparatus: A mask circuit (2) masks a bit sequence of K bits by a predetermined bit pattern. An EXOR circuit (3) EXORs the masked bit sequence. An inverter (9) controls inversion/non-inversion of values of bits of a bit sequence which includes a bit value indicating the EXOR result in a result...

20050278403 - Numerically controlled oscillator and method of operation: In one embodiment, the present invention is directed to a numerically controlled oscillator. The numerically controlled oscillator comprises: a phase accumulator for receiving an input digital word; and a phase to amplitude converter that is operatively coupled to the phase accumulator to receive a first phase signal and a second...

20050278405 - Fourier transform processor: The present invention is two-iteration Fourier transform processor for performing Fourier transform of N data inputs into N data outputs. The processor comprises a plurality of two-iteration radix-r modules and a combination phase element. Each radix-r module comprises r radix-r butterflies, a feedback network and a plurality of switches. Each...

20050278404 - Method and apparatus for single iteration fast fourier transform: The present invention is single-iteration Fourier transform processor. A Fourier transform processor performs Fourier transform of N input data into N output data with a radix-r butterfly. The Fourier transform processor includes N/r radix-r modules. Each radix-r module includes a plurality of radix-r engines, and each radix-r engine includes a...

20050278406 - System and computer-implemented method for evaluating integrals using stratification by rank-1 lattices: A system for numerically evaluating an integral of a function over an s-dimensional integration domain is described, the system comprising a sample point generator, a function value generator and an integral value estimate generator. The sample point generator is configured to generate a selected number of sample points over the...

20050278407 - Addressing type of asynchronous divider: The present invention relates to an addressing type of asynchronous divider that uses addressing system, which enables an external circuit to receive a divisor and a dividend. Through the process of addressing type of asynchronous divider, the calculated quotient and remainder are transferred to the external circuit using addressing system....

20050273477 - Method of discretion of a source attribute of a database: A method of discretization/grouping of a source attribute or of a source attributes group of a database containing a population of individuals with the object in particular of predicting modalities of a given target attribute. The method includes the steps of: a) partitioning of the modalities of the source attribute...

20050273478 - Apparatus, system, and method for efficient and reliable computation of results for mathematical functions: An apparatus, system, and method are provided for efficient computation of reliable results for mathematical functions. The apparatus may include an interface, a control module, and an error module. The interface receives a mathematical function call. The call includes a plurality of arguments for which a range of computable results...

20050273479 - Reformulation of the finite-difference time-domain algorithm for hardware-based accelerators: A hardware-based acceleration platform for computational electromagnetic algorithms, specifically the finite-difference time-domain (“FDTD”) method, comprises reformulating the FDTD algorithm in order to make it more hardware friendly. This reformulation makes use of split fields at every node in the mesh, and combines total- and scattered-field formulations into a single, hybrid...

20050273480 - Gold code generator design: A gold code generator is described comprising two pairs of linear feedback shift registers, the seed values for the second pair of linear feedback shift registers are different from the seed values for the first pair of linear feedback shift registers. The second seed values are calculated from the first...

20050273481 - Pipelined real or complex alu: A method and ALU for implementing logarithmic arithmetic in a multi-stage pipeline is described herein. According to one embodiment, a master function is decomposed into two or more sub-functions. Memory associated with the pipeline stores a look-up table for each stage of the pipeline, where each table represents function values...

20050273482 - Digital filter and method thereof using frequency translations: A digital filter and method of filtering frequency translate or shift a spectrum of a digital input signal and further filter a translated signal to reduce or attenuate frequency components in the spectrum of the input signal. The digital filter includes first and second translators and a first filter. The...

20050273483 - Complex logarithmic alu: The present invention describes a method and apparatus for performing logarithmic arithmetic with real and/or complex numbers represented in a logarithmic format. In one exemplary embodiment, an ALU implements logarithmic arithmetic on complex numbers represented in a logpolar format. According to this embodiment, memory in the ALU stores a look-up...

20050273484 - Method and apparatus for processing multiple decomposed data for calculating key equation polynomials in decoding error correction code: The invention is a method of calculating a key equation polynomial. The key equation comprises an errata locator polynomial and an errata evaluator polynomial. The errata locator polynomial decomposes to a plurality of coefficients. Some or all of the plurality of coefficients are formed by adding up decomposed data. The...

20050273485 - Polynomial and integer multiplication: A method and apparatus for generating a plurality of concurrent significant bits forming at least a portion of a product from at least two partial products, the method comprising the following steps: for each of a plurality of said concurrent predetermined significant bits performing steps (i) to (iii): (i) performing...

20050267924 - Interpolation filter design and application: A method for designing an interpolation filter begins by partitioning interpolation filtering into a plurality of interpolation filtering stages that are cascaded together. Each of the plurality of interpolation filtering stages includes an up sampling stage and a filtering stage. The method continues by manipulating a first one of the...

20050267925 - Methods and apparatus for transforming amplitude-frequency signal characteristics and interpolating analytical functions using circulant matrices: A method of performing a direct discrete transformation of a signal includes reading amplitude-frequency characteristics of a signal from a sensor. The signal is associated with a base grid to form a digital representation of a function that has a discrete Fourier representation. A circulant matrix is calculated that represents...

20050267926 - Finite field serial-serial multiplication/reduction structure and method: The present invention contemplates a method or cryptographic system for communicating securely over an insecure communication channel of the type which communicates a message from a transmitter to a receiver. The method includes the step of providing a finite filed serial-serial multiplication/reduction structure wherein an initial delay and clock-cycle are...