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12/14/06 - USPTO Class 712 |  9 views | #20060282650 | Prev - Next | About this Page  712 rss/xml feed  monitor keywords

Efficient clip-testing

USPTO Application #: 20060282650
Title: Efficient clip-testing
Abstract: A method and apparatus for performing fast clip-testing operations in a general purpose processor are provided. This is accomplished by executing a single instruction for comparing a first value x to a second value y and, as a result of the comparison, determining whether x is less than y and whether x-is less than negative y. The values x and y are stored in respective source registers of the processor specified by the instruction. Finally, as a result of the determination, one or more binary values representing the results of the determination are inserted into a destination register of the processor also specified by the instruction. Accordingly, the invention advantageously provides a general purpose processor with the ability to execute a clip-testing function with a single instruction compared with prior art general purpose processors that require multiple instructions to perform the same function. Thus, the general purpose processor of the present invention allows for more efficient and faster clip-testing operations. (end of abstract)



Agent: Zagorin O'brien Graham LLP (004) - Austin, TX, US
Inventors: Jeffrey Meng Wah Chan, Michael F. Deering, Marc Tremblay
USPTO Applicaton #: 20060282650 - Class: 712221000 (USPTO)

Related Patent Categories: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors), Processing Control, Arithmetic Operation Instruction Processing

Efficient clip-testing description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20060282650, Efficient clip-testing.

Brief Patent Description - Full Patent Description - Patent Application Claims
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CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

[0001] This patent application is a continuation of co-pending U.S. patent application Ser. No. 09/589,039, filed Jun. 6, 2000, naming as inventors Jeffrey Meng Wah Chan, Michael F. Deering, and Marc Tremblay, which in turn is a continuation of U.S. Pat. No. 6,718,457, filed Dec. 3, 1998, naming as inventors Marc Tremblay and William Joy, which is incorporated by reference herein in its entirety.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates generally to processors and, more particularly to instructions for use with processors.

[0004] 2. Related Art

[0005] The increasing popularity of multimedia and 3-D graphics display has created a substantial demand for current microprocessors to support graphics operations. Typically, this is done by means of surface graphics techniques, where an object is represented as a collection of very small primitives, simple geometric shapes such as triangles that approximate the shape of the object. Each of the triangles is represented by a set of vertices whose coordinates are stored in the memory of a computer. In addition to the coordinates of the vertices, additional information pertaining to color, lighting and other properties of the triangles are also stored in the memory of the computer. In order to display the objects represented by the triangles, a series of mathematical transformations are applied to the data stored in the memory of the computer to transform the three-dimensional representation of the object into a two-dimensional image that can be displayed on a screen of the computer. One of the operations required as part of these transformations is a determination of which triangles or portions of the triangles are visible from the viewpoint chosen for the displayed image. This operation is known as clip-testing. An important element of a clip-testing operation is determining whether a point at a given set of coordinates is within the eye space visible on the screen.

[0006] While dedicated graphics processors such as DSPs provide varying levels of hardware support for clip-testing operations, general purpose processors typically provide only limited support for clip-testing operations, thereby requiring these operations to be performed by software executing on the processor. Since hardware implementations are inherently faster than software implementations, there is a need for a general purpose processor that supports faster clip-testing operations.

SUMMARY OF THE INVENTION

[0007] The present invention provides a method and apparatus for performing fast clip-testing operations in a general purpose processor. The fast clip-testing operations are accomplished by executing a single instruction for comparing a first value x to a second value y and, as a result of the comparison, determining whether x is less than y and whether x is less than negative y. The values x and y are stored in respective source registers of the processor specified by the instruction. As a result of the determination, one or more binary values representing the results of the determination are inserted into a destination register of the processor also specified by the instruction.

[0008] Accordingly, the invention advantageously provides a general purpose processor with the ability to execute a clip-testing function with a single instruction compared with prior art general purpose processors that require multiple instructions to perform the same function. Thus, the general purpose processor of the present invention allows for more efficient and faster clip-testing operations.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1A is a schematic block diagram illustrating a single integrated circuit chip implementation of a processor in accordance with an embodiment of the present invention.

[0010] FIG. 1B is a schematic block diagram showing the core of the processor.

[0011] FIG. 2A is a diagrammatic block diagram of a register file of the processor of FIG. 1B.

[0012] FIG. 2B is a diagrammatic block diagram of a register of the register file of FIG. 2A.

[0013] FIG. 3A is a diagrammatic block diagram showing instruction formats for four operand instructions supported by the processor of FIG. 1B.

[0014] FIG. 3B is a diagrammatic block diagram showing an instruction format for a clip-testing instruction supported by the processor of FIG. 1B.

[0015] FIG. 4 is a diagrammatic block diagram showing the relationship between the instruction format of FIG. 3B and the register file of FIG. 2A.

[0016] FIG. 5 is a block diagram of one implementation of the circuitry within MFUs 222 of the processor of FIG. 1B for performing the clip-testing instruction of FIG. 3B.

[0017] FIG. 6 is a block diagram of an alternative implementation of the circuitry within MFUs 222 of the processor of FIG. 1B for performing the clip-testing instruction of FIG. 3B.

DETAILED DESCRIPTION OF THE INVENTION

[0018] A processor in accordance to the principles of the present invention is illustrated in FIG. 1A and 1B.

[0019] Referring to FIG. 1A, a schematic block diagram illustrates a single integrated circuit chip implementation of a processor 100 that includes a memory interface 102, a geometry preprocessor 104, two media processing units 110 and 112, a shared data cache 106 and several interface controllers. The components are mutually linked and closely linked to the processor core with high bandwidth, low-latency communication channels to manage multiple high-bandwidth data streams efficiently and with a low response time.

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Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)

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