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  Dynamic pre-charge level control in semiconductor devicesUSPTO Application #: 20060164904Title: Dynamic pre-charge level control in semiconductor devices Abstract: Dynamic control of a pre-charge level particularly for memory cells is described. In one example, a circuit block has pre-charge node and a power supply is coupled to the pre-charge node to provide either a first power level or a second power level when the circuit block is not active. The first power level may be a pre-charge mode power level and the second power level may be a sleep mode power level. (end of abstract)
Agent: Blakely Sokoloff Taylor & Zafman - Los Angeles, CA, US Inventor: Hugo Saleh USPTO Applicaton #: 20060164904 - Class: 365226000 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20060164904. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND [0001] 1. Field [0002] The present description relates to dynamically controlling a pre-charge level in a semiconductor device, and in particular to applying at least two different pre-charge levels to reduce gate leakage and power consumption. [0003] 2. Background [0004] Semiconductor devices, such as transistors, diodes and capacitors experience current leakage. The leakage can occur in gates and other components of semiconductor devices. The leaked current generates heat so that power consumption and cooling requirements are increased. In some circumstances, current leakage can diminish signal fidelity or capacity. The leakage current can also affect other nearby devices. As a result, semiconductor systems, such as microprocessors, CPUs (Central Processing Units), ASICs (Application Specific Integrated Circuits), FPGAs (Field Programmable Gate Arrays), DSPs (Digital Signal Processors), and memory arrays, among others are often designed with an intent to reduce leakage and to guide leakage current away from sensitive portions of the semiconductor circuitry. [0005] In memory arrays, there is significant leakage at bit-line gates and word-line gates. Many memory cell designs require constant power to maintain a memory state and to allow the memory to be read or written to. The leakage current increases the power consumption of the memory array whether or not the memory is being used. In the design of microprocessors, this leakage current has been considered to be insignificant and has been managed primarily by protecting sensitive devices from it. However, as the amount of cache memory in microprocessors increases and as the size of the transistors and other devices is reduced, the amount of leakage current in a microprocessor is increased. Similarly, the power consumed by leakage current in any large memory array increases as the number of memory cells and the cell density is increased. BRIEF DESCRIPTION OF THE DRAWINGS [0006] Embodiments of the present invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention. The drawings, however, should not be taken to be limiting, but are for explanation and understanding only. [0007] FIG. 1 is a diagram of a 6T SRAM memory cell showing some current leakage paths; [0008] FIG. 2 is a circuit diagram of a memory cell with controllable pre-charge according to an embodiment of the present invention; [0009] FIG. 3 is a timing diagram of voltage at selected places in the circuit of FIG. 2; [0010] FIG. 4 is a circuit diagram of a sub-array of memory cells with controllable pre-charge according to an embodiment of the present invention; [0011] FIG. 5 is a block diagram of control and distribution logic for pre-charge selection for a group of memory sub-arrays according to an embodiment of the present invention; [0012] FIG. 6 is a block diagram of control and distribution logic for pre-charge selection for banks of memory sub-arrays according to an embodiment of the present invention; [0013] FIG. 7 is a block diagram of a microprocessor architecture to which embodiments of the present invention may be applied; and [0014] FIG. 8 is a block diagram of a computer system to which embodiments of the present invention may be applied. DETAILED DESCRIPTION [0015] One common type of memory cell is a 6T SRAM (Six Transistor Static Random Access Memory) 10, shown, for example in FIG. 1. In one configuration, the memory has two bit-lines 12 that are held in a pre-charge high voltage (Vdd/Vcc) state by two corresponding pre-charged voltage supply circuits 20. The memory cell also has word-lines 14 that allow the memory to be read from or written to. In the conventional CMOS (Complementary Metal Oxide Semiconductor) 6T SRAM cell, there are two word-line NMOS (Negative channel MOS) pass transistors 16. The sources of the NMOS word-line transistors are coupled to the bit-lines and the drains are coupled to opposite sides of a four transistor storage cell 17. The storage cell has two PMOS (Positive channel MOS) transistors with sources held high at Vdd/Vcc, and with drains each coupled to a drain of an NMOS transistor. The sources of the NMOS transistors are grounded. [0016] There is a word-line junction coupling the drain of each word-line transistor 16 to the junction between drains of a respective PMOS, NMOS transistor pair.. This junction is also coupled to the gates of the other PMOS, NMOS transistor pair. The operation of the bit-lines and word-lines of such a conventional 6T SRAM memory cell has been well documented. [0017] Such a memory cell has several current leakage paths. One path is from the PMOS transistor that is ON onto the word-lines 14, as indicated by arrow 22. However, the largest leakage current path is from the pre-charge devices 20 through the bit-lines 12 through the NMOS pass transistors 16, and onto the word-line drivers as indicated by arrows 24. The excess current from the word-lines accumulates at decoders 18 that operate on the word-lines. In some systems, this leakage current may be on the order of 45 nA (30 nA from the bit-lines and 15 nA from the memory cell) for each memory cell. With a 2 MB cache memory this leakage adds up to about 0.85 A or about 1.0 W. As the number of memory cells increases with new CPU designs and as transistor gate leakage increases with new, denser processes, the effects of this leakage becomes more noticeable. These leakage paths are the second largest contributor to cache standby power consumption after inherent memory cell gate leakage. [0018] These current leakage paths lead to power dissipation and reduced reliability for the word-line drivers and memory cell NMOS pass devices in the path. Because the NMOS devices are continuously conducting the leakage current, the NMOS devices are worn more than other NMOS devices in a semiconductor system. In a CMOS logic system, the NMOS logic devices are conducting current only when they switch, but in a large memory cache, NMOS devices in the word-line drivers will constantly be conducting current to ground due to this leakage path. The NMOS devices of a large memory cache may accordingly fail before the NMOS devices of a corresponding logic system. [0019] The leakage currents can be reduced by reducing the pre-charge voltage on the bit-lines from the standard supply voltage (Vdd/Vcc) to a lower value. The parasitic gate leakage which generates the leakage path has a strong voltage dependence. By reducing the voltage by the threshold voltage (Vtn) of the NMOS devices, for example, the power consumption due to leakage can be reduced in half. Larger voltage reductions will further reduce power consumption. The best voltage reduction value will depend upon the particular circuit design, fabrication process, and intended use. [0020] By dynamically changing the voltage level applied to the bit-lines, memory array standby power can be reduced at the same time that word-line driver reliability is improved. In one embodiment, the invention uses NMOS sleep devices in addition to PMOS pre-charge devices to reduce the bit-line pre-charge level when the array is not being accessed (bit-line sleep mode). Control logic switches from a sleep mode to a pre-charge mode when the corresponding memory cell is to be accessed. The control logic can also ensure that the two modes are mutually exclusive. [0021] Referring to FIG. 2, a 6T SRAM (Six Transistor Static Random Access Memory) 210, similar to that of FIG. 1, has bit-lines 212 that are held in a pre-charge high voltage (Vdd/Vcc) state when the array is not being accessed. The two word-lines 214 are coupled through two word-line NMOS (Negative channel MOS) pass transistors 216 and to opposite sides of a four transistor storage cell 217. Continue reading... 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