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Dual phase shift photolithography masks for logic patterningRelated Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Design Of Semiconductor MaskDual phase shift photolithography masks for logic patterning description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060225025, Dual phase shift photolithography masks for logic patterning. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND [0001] 1. Field [0002] The present description relates to semiconductor photolithography and, in particular, to generating alternating phase shift photolithography masks. [0003] 2. Background [0004] In the production of semiconductors, such as memory, processors, and controllers, among others, a mask is used. The mask pattern is projected onto a semiconductor wafer to expose or shield different portions of the wafer from light, or some other element. The exposed wafer is then processed with etching, deposition and other processes to produce the features of the various semiconductors in the wafer that make up the finished product. [0005] The masks are designed using computer design programs that derive an aerial view or image of the wafer based on the electronic circuitry that is to be built on the wafer. The mask is designed to produce this aerial image on the wafer in the particular photolithography equipment that is to be used. In other words the mask must be designed so that when illuminated with a particular wavelength of light at a particular distance is directed to a wafer through a particular set of optics and the mask, the desired pattern will be formed with the desired intensity on the wafer. [0006] By making the features on a semiconductor smaller, more and faster processing power can be provided in a smaller space. At the same time the energy consumed and the heat produced by the chip is reduced. Smaller features require higher resolution from the mask and optical system that creates the pattern on the wafer. Resolution enhancement techniques (RET) are used to create smaller patterns. [0007] Alternating phase shift masks (APSM) is one type of RET. It uses two independent exposures. For APSM, the design layout pattern is broken up into two independent layers. The first layer is converted to an APSM by an algorithm which assigns phases to create the desired pattern. In general, a complex pattern cannot be assigned phases without conflicts. A phase conflict can result in error in the printing of the features. These phase conflicts are corrected by a second exposure using a trim mask that removes most of the phase conflict errors but limits the resolution. [0008] Optical proximity correction (OPC) is also used to enhance resolution and accuracy for small features. In OPC, the mask pattern is supplemented with very small subresolution features that are used to improve the accuracy with which the pattern is actually produced by the photoresist. These features may include pattern decorations and scatter bars. While the quality of the pattern and the performance of the resulting circuit is improved, the resolution is not significantly increased. BRIEF DESCRIPTION OF THE DRAWINGS [0009] Embodiments of the present invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention. The drawings, however, should not be taken to be limiting, but are for explanation and understanding only. [0010] FIG. 1 is a diagram of a semiconductor fabrication device suitable for application to the present invention; [0011] FIG. 2 is a process flow diagram of a modifying a mask according to an embodiment of the present invention; [0012] FIG. 3 is another process flow diagram of a modifying a mask according to an embodiment of the present invention; and [0013] FIG. 4 is an example of a computer system capable of performing aspects of the present invention. DETAILED DESCRIPTION [0014] As described below, any layout of logic or memory circuit photolithography patterns may be converted into two optimal phase shift masks, based on a complex representation of the corresponding coherent imaging electric field. The electric field may be iterated in the complex plane and the image intensity (the squared modulus of the electric field) may be monitored for convergence to the input layout or intended design. [0015] The two phase shift masks may be obtained by decomposing the converged imaging electric field into real and imaginary parts, with the real component of the electric field determining one phase mask, and the imaginary component of the electric field determining the other phase mask. Each phase mask is obtained by contouring the real or imaginary component at various electric field thresholds and may be further optimized by modifying the contours to improve the pattern fidelity. The process may be referred to as optimal since it may be used to create a pattern through photolithography which is at or near the limit of optical resolution (e.g. at a k1 factor of 0.25 which corresponds to a half pitch equal to 0.25 times the wavelength divided by the NA of the stepper). [0016] The exposure of the photoresist on the wafer records the intensity (square of the electric field amplitude) projected into the resist. The photoresist is exposed first by one mask and then by the other mask in order to obtain the final pattern. The decomposition of the image intensity can be split uniquely into two exposures, one exposure for the square of the real part of the complex electric field and the other for the square of the imaginary part of the complex electric field. Using real and imaginary parts of the imaging electric field to construct the two masks allows for the elimination of phase conflicts. [0017] The computation of the coherent complex electric field incident on the wafer may be obtained using the methods of Fourier optics. The initial complex field estimate is constructed by taking the mask layout as a binary mask and evaluating the coherent image for the stepper (e.g. at the numerical aperture, NA). The target complex electric field is obtained by considering the mask layout as a binary mask and evaluating the coherent image for an artificial stepper with higher resolution, namely 2NA. The iterated complex electric field amplitude is compared to the target amplitude and monitored for convergence. [0018] Once the convergence criteria has been satisfied, the iteration stops and the last iteration is taken as the optimal complex electric field. Each of the masks is constructed by contouring the continuous real or imaginary electric fields at thresholds set by the maximum and minimum amplitude values. The resulting electric field contours are assigned transmission and phase values; mask transmission 1 (phase 0 degrees), mask transmission -1 (phase 180 Degrees), and mask transmission 0 (chrome). The contour polygons represent the new optimal mask layout and may be further optimized by dividing each contour into a series of segments and moving each segment in such a way as to improve the overall image fidelity, as in a standard OPC procedure. [0019] FIG. 1 shows a conventional semiconductor fabrication machine, in this case, a lens-scanning ArF Excimer Laser Stepper. The stepper may be enclosed in a sealed vacuum chamber (not shown) in which the pressure, temperature and environment may be precisely controlled. The stepper has an illumination system including a light source 101, such as an ArF excimer laser, a scanning mirror 103, and a lens system 105 to focus the laser light on the wafer. A reticle scanning stage 107 carries a reticle 109 which holds the mask 111. The light from the laser is transmitted onto the mask and the light transmitted through the mask is focused further by a projection lens with, for example, a four fold reduction of the mask pattern onto the wafer 115. [0020] The wafer is mounted to a wafer scanning stage 117. The reticle scanning stage and the wafer scanning stage are synchronized to move the reticle and the wafer together across the field of view of the laser. In one example, the reticle and wafer move across the laser light in a thin line, then the laser steps down and the reticle and wafer move across the laser in another thin line until the entire surface of the reticle and wafer have been exposed to the laser. Such a step and repeat scanning system allows a high intensity narrow beam light source to illuminate the entire surface of the wafer. The stepper is controlled by a station controller (not shown) which may control the starting, stopping and speed of the stepper as well as the temperature, pressure and chemical makeup of the ambient environment, among other factors. The stepper of FIG. 1 is an example of a fabrication device that may benefit from embodiments of the present invention. Embodiments of the invention may also be applied to many other photolithography systems. [0021] The mask controls the size of each feature on the wafer. The mask design is made up of chrome metal lines or lines of some other material of different widths and shapes designed to create a particular pattern on the wafer. When OPC (Optical Proximity Correction) is applied to the mask, the mask is modified iteratively, primarily by modifying the widths of the metal lines and adding decorations to corners, until the photolithography model predicts that the final wafer will match the intended target design. Then the physical model is used to adjust the chrome size on the mask to achieve the new desired size on the wafer. Continue reading about Dual phase shift photolithography masks for logic patterning... Full patent description for Dual phase shift photolithography masks for logic patterning Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Dual phase shift photolithography masks for logic patterning patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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