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  Dual gate oxide structure in semiconductor device and method thereofUSPTO Application #: 20070246779Title: Dual gate oxide structure in semiconductor device and method thereof Abstract: In the method of manufacturing a dual gate oxide layer of a semiconductor device, which has first and second active regions operating at mutually different voltages on a semiconductor substrate, the first and second active regions having a device isolation layer of STI (Shallow Trench Isolation) structure; the method of manufacturing the dual gate insulation layer includes, forming the device isolation layer so that an uppermost part thereof is positioned lower than an upper surface of the first and second active regions, before forming a gate insulation layer corresponding to each of the first and second active regions. Whereby, it is be effective till a portion of trench sidewall utilized as the active region, to increase a cell current of the active region and to prevent a stringer caused by a stepped coverage between the active region and a field region and a dent caused on a boundary face between the active region and the field region. (end of abstract) Agent: Marger Johnson & Mccollom, P.C. - Portland, OR, US Inventors: Jong-Sik CHUN, Hyun-Ho JO, Byung-Hong CHUNG USPTO Applicaton #: 20070246779 - Class: 257365000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), With Plural, Separately Connected, Gate Electrodes In Same Device The Patent Description & Claims data below is from USPTO Patent Application 20070246779. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of U.S. patent application Ser. No. 10/876,277, filed Jun. 23, 2004, now pending, which is claims priority from Korean Patent Application No. 2003-0040714, filed on Jun. 23, 2003, the disclosure of which are incorporated herein in its entirety by reference. FIELD OF THE INVENTION [0002] This disclosure relates to a semiconductor device, and more particularly, to a method of forming a dual gate oxide having oxide layers based on different thickness in different voltage regions. PRIOR ART OF THE INVENTION [0003] In a semiconductor memory device such as an SRAM etc., an operating voltage of a transistor constituting a memory cell and an operating voltage of transistor positioned within a peripheral logic circuit to access data of the memory cell are typically different from each other, thus a thickness of gate insulation layers, e.g., oxide layers, are also different. Further, in the field of power devices such as LDI (LCD Driver IC) products, a low voltage operation for driving a logic circuit and a high voltage operation for driving an LCD are all necessary in a driving device, thus a gate oxide layer should have a dual gate structure and an employment for a shallow trench isolation (STI) structure based on a reduction of line width, which is also tending to be used. [0004] However, in applying a dual gate oxide to the STI structure using manufacturing processes of the prior art, an uppermost part of the device isolation layer is positioned higher than an upper surface of active region, which causes a stepped coverage therebetween. If the stepped coverage occurs, a portion of trench sidewall ca not be used as the active region, and a stringer occurs due to the stepped coverage between the active region and the field region. This also causes a relatively severe dent on a boundary face between the active region and the field region owing to a wet etching rate difference between materials of a field oxide layer formed in the STI and a thermal oxide layer formed in the active region. [0005] The dual gate oxide manufacturing process of the prior art will be described referring to FIGS. 1a through 1f in order to thoroughly understand the causes of the above-mentioned phenomena. [0006] Referring to FIGS. 1a to 1f illustrating a process sequence, a method of forming dual gate oxide according to the prior art will be described in detail. Herewith, the process will be described with six steps for the explanatory convenience. In the drawings, reference character I indicates a low voltage (LV) region of a substrate as a first active region on which a thinned gate oxide will be formed, and reference character II designates a high voltage (HV) region as a second active region on which a thick gate oxide will be formed. [0007] In a first step, as shown in FIG. 1a, a pad oxide layer 102 and a nitride layer 104 are accumulated sequentially on a semiconductor substrate 100 to form a layer 105. Next, on the nitride layer 104, a photoresist pattern 109 is formed which will expose a portion where a trench for defining the first active region I and the second active region II will be formed, and a portion where a trench for a device isolation of each active region will be formed. [0008] In a second step, as shown in FIG. 1b, the nitride layer 104, the pad oxide layer 102 and the semiconductor substrate 100 are etched sequentially by using the photoresist pattern 109 as an etch mask, to form a trench t1 for defining the first active region I and the second active region II on the semiconductor substrate 100, and to form a trench t2 for isolating devices on each active region. Then, the remaining photoresist pattern 109 is removed through an ashing process. [0009] In a third step, as shown in FIG. 1c, a field oxide layer 108 is formed of a USG (Undoped Silicate Glass) or HDP (High Density Plasma) material, to completely fill up the trenches t1, t2. Further, a flattening process such as a CMP (Chemical Mechanical Polishing) etc. for the field oxide layer 108 and the nitride layer 104 is performed so that a nitride layer pattern 107 partially remains on the first and second active regions I, II, to thus form first and second device isolation layers 110, 112 for filling the trenches t1, t2. The first device isolation layer 110 is defined as a layer to isolate between the first and second active regions and the field region, and the second device isolation layer 112 is defined as a layer to isolate devices of each active region. [0010] In a fourth step, as shown in FIG. 1d, the remaining nitride layer 107 is removed by a wet etching using H.sub.3PO.sub.4, and the pad oxide layer 102 is removed by a wet etching using a diluted HF, to thus expose the surface of the first and second active regions I, II. Subsequently, a first thermal oxide layer 114 of 300 .ANG. for high voltage use is formed on the surface exposed portion of the First and second active regions I, II. [0011] In a fifth step, as shown in FIG. 1e, a photoresist pattern 111 for exposing the first active region I and a portion of the first device isolation layer 110 is formed, and then, the first thermal oxide layer is etched by using the photoresist pattern 111 as an etch mask, to selectively leave the first thermal oxide layer 114 only on the second active region II. [0012] In a sixth step, as shown in FIG. 1f, the photoresist pattern 111 is removed by an ashing process, and a second thermal oxide layer 116 of 40 .ANG. for use of low voltage is formed on the first active region I, to thus complete a dual gate oxide layer process. Of course, in forming the second thermal oxide layer 116, the first thermal oxide layer 114 also grows an insignificant amount. [0013] As the result of that process, the thinned gate oxide layer 116 of second thermal oxide material for use of a low voltage is formed on the first active region I, and the thick gate oxide layer 114 of first thermal oxide material for use of a high voltage is formed on the second active region II. [0014] Even though this structure of dual gate oxide layer based on the prior art can increase an integration of device, a size of active region has a fixed structure, and an upper part of STI is positioned higher than an upper part of the active region, causing a stepped structure, thus there are many problems as follows. [0015] First, since the upper part of STI is positioned higher than an upper part of the active region, i.e., the stepped structure, a trench sidewall portion can not be used as the active region, which cause the active region to have a fixed size. [0016] Also, in a subsequent gate etching process, a stringer based on the stepped coverage between an active region and a field region is caused. [0017] Further, the STI is formed of field oxide material such as USG or HDP etc., and the gate oxide layer is formed of thermal oxide material, thus in using an etching process to form the dual gate oxide layer, a severe dent is caused on a boundary face between the active region and the field region owing to a wet etching rate difference between the field oxide layer and the thermal oxide layer. [0018] Embodiments of the invention address these and other limitations of the prior art. SUMMARY OF THE PRESENT INVENTION [0019] Example embodiments of the present invention provide a dual gate oxide structure in a semiconductor device and a method of forming the structure, which is capable of extending an area of active region by utilizing a trench sidewall portion of device isolation layer as the active region. Herewith, a cell current of active region can increase to enhance a characteristic of device. In addition, a stringer causable by a stepped coverage between an active region and a field region can be prevented, and it can be prevented a dent causable on a boundary face between the active region and the field region owing to a wet etching rate difference between field oxide material formed on a STI and thermal oxide material formed on the active region. [0020] According to an exemplary embodiment of the present invention, a method of forming a dual gate oxide layer includes, sequentially accumulating a first insulation layer and a second insulation layer on a semiconductor substrate; sequentially etching the second insulation layer, the first insulation layer and a portion of the semiconductor substrate, and forming a trench for defining first and second active regions on the semiconductor substrate; filling up the trench with a field oxide layer, and then, flattening the field oxide layer and the second insulation layer so that the second insulation layer accumulated on the first insulation layer remains by a determined thickness, to thus form a device isolation layer; removing the remaining second insulation layer, and etching the first insulation layer and the device isolation layer in such a way that an uppermost part of the device isolation layer is positioned below an upper surface of the first and second active regions; forming a first thermal oxide layer for use of a gate oxide layer on the first and second active regions; and removing the first thermal oxide layer provided with the first active region, and then, forming a second thermal oxide layer for use of a gate oxide layer on the first active region, the second thermal oxide layer having a thickness thinner than the first thermal oxide layer. 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