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  Dual-edge shaping latch/synchronizer for re-aligning edgesUSPTO Application #: 20070176662Title: Dual-edge shaping latch/synchronizer for re-aligning edges Abstract: Integrated circuit and process for aligning a first signal with a second signal. The integrated circuit includes a single latch, a switch control circuit coupled to an input of the single latch to align an edge of the first signal with an edge of the second signal, and a second switch control circuit coupled to the output of the single latch to produce a 50% duty cycle output. (end of abstract)
Agent: Greenblum & Bernstein, P.L.C - Reston, VA, US Inventor: Christopher W. Scoville USPTO Applicaton #: 20070176662 - Class: 327291000 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20070176662. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The instant invention relates to a process and device to re-align/synchronize edges of two periodic signals, in which one is either an integer multiple of the other or of the same frequency. BACKGROUND DESCRIPTION [0002] A desired feature in some phase locked loops (PLL) is aligning a clocked output and a divided down (in frequency) version of the clock, e.g., to align two clocks which are integer multiples of each other. In the known art, simple dual latch designs have been utilized, however, these designs do not preserve the 50% duty ratio for odd divide ratios. Moreover, alignment of the clock signals has been difficult due to delay through the clock dividers as the result of temperature, voltage operating range, and processing. [0003] As shown in FIG. 1, a clock signal (Clock A) can be applied to a divider 11, e.g., a 2-8 divider, to produce an output Clock B. Thus, Clock B is derived from a divided down earlier version of Clock A. However, as discussed above, delay through divider 11 can vary, e.g., due to temperature, voltage, processing. A graphical representation of this delay is shown in FIG. 2, in which the rising edge of the output from the divider CLOCK B is delayed from the rising edge of the input to the divider CLOCK A. Further, the delay in the divider may be different depending upon the divide ratio. By way of example, for even divide ratios, the delay may be, e.g., 97 picoseconds, while for odd divide ratios, the delay may be, e.g., 94 picoseconds. As a result, up to a 400 picosecond delay may be achieved over all divide ratios. Moreover, with arrangement shown in FIG. 2, CLOCK B for odd divide ratios does not have a 50% duty cycle. SUMMARY OF THE INVENTION [0004] The present invention is directed to an integrated circuit capable of aligning a first signal with a second signal. The integrated circuit includes a single latch and a switch control circuit coupled to an input of the single latch to align an edge of the first signal with an edge of the second signal with a 50% duty cycle output. [0005] In accordance with a feature of the invention, the second signal is a divided ratio of the first signal. Further, the first and second signals can have a same frequency. [0006] Further, the invention is directed to a process for aligning a first signal with a second signal. The process includes applying the second signal to an input of a single switch shaping latch and aligning an edge of the second signal with an edge of the first signal. An output of the single switch shaping latch has a 50% duty cycle output. [0007] The instant invention is directed to a clock signal synchronization device that includes a shaping latch composed of a single switch. [0008] According to a feature of the invention, the device can further include a divider, arranged to output a divided ratio of a clock signal, coupled to the shaping latch. The shaping latch aligns the edges of the clock signal with edges of the divided ratio of the clock signal. Further, the divider can be an adjustable divider. The divided ratio of the clock signal may be an even divided ratio or the divided ratio of the clock signal may be an odd divided ratio. [0009] In accordance with another feature of the invention, the switch can be a CMOS switch. Further, the divider may create a delay in the divided ratio of the clock signal with respect to the clock signal of between 0 and 1/2 a clock cycle. In this situation, the clock signal can be inverted before being input to the divider. Moreover, the divider may create a delay in the divided ratio of the clock signal with respect to the clock signal of between 1/2 a clock cycle and a full clock cycle. In this situation, the clock signal can be input directly into the divider. [0010] According to still another feature of the present invention, the shaping latch can align the edges of the two clock signals having a same frequency. The shaping latch may create a delay between a reference clock signal and a clock signal to be aligned. [0011] The shaping latch can align the edges of the two clock signals having a different frequency. Moreover, the different frequencies can be multiples of each other. [0012] The present invention is directed to a process for synchronizing a first clock signal with a second clock signal, in which edges of the second clock signal are not aligned with edges of the first clock signal. The process includes aligning the edges of the second clock signal with the edges of the first clock signal through a shaping latch composed of a single switch. [0013] According to a feature of the invention, the process can further include dividing the first clock signal in a divider to form the second clock signal. In this regard, the second clock signal can be an even divided ratio of the first clock signal, or the second clock signal can be an odd divided ratio of the first clock signal. [0014] In accordance with another feature of the invention, the second clock signal may have a different frequency than the first clock signal. Further, the second clock signal can be a multiple of the first clock signal. [0015] According to still yet another feature of the present invention, the first and second clock signals may have a same frequency. Further, the shaping latch can create a delay between a first clock signal and the second clock signal. The process can also include delaying the first clock signal. BRIEF DESCRIPTION OF THE DRAWINGS [0016] FIG. 1 schematically illustrates a clock signal and a divided ratio of the clock signal; [0017] FIG. 2 schematically illustrates the delay in the divided clock signal; [0018] FIG. 3 schematically illustrates a shaping latch in accordance with the instant invention; [0019] FIG. 4 schematically illustrates an example application of the shaping latch of the instant invention; [0020] FIG. 5 schematically illustrates a shaping latch in accordance with the present invention; Continue reading... Full patent description for Dual-edge shaping latch/synchronizer for re-aligning edges Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Dual-edge shaping latch/synchronizer for re-aligning edges patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Dual-edge shaping latch/synchronizer for re-aligning edges or other areas of interest. ### Previous Patent Application: Data delay control circuit and method Next Patent Application: Offset signal phasing for a multiple frequency source system Industry Class: Miscellaneous active electrical nonlinear devices, circuits, and systems ### FreshPatents.com Support Thank you for viewing the Dual-edge shaping latch/synchronizer for re-aligning edges patent info. IP-related news and info Results in 0.07248 seconds Other interesting Feshpatents.com categories: Electronics: Semiconductor , Audio , Illumination , Connectors , Crypto , |
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