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Dual-damascene process to fabricate thick wire structureRelated Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Including Passive Device (e.g., Resistor, Capacitor, Etc.), Capacitor, Stacked CapacitorDual-damascene process to fabricate thick wire structure description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070190718, Dual-damascene process to fabricate thick wire structure. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The invention generally relates to a semiconductor device and method of manufacture and, more particularly, to a semiconductor device having analog, or super thick, wires and a method of manufacturing thereof using a dual-damascene process. BACKGROUND OF THE INVENTION [0002] Super thick damascene copper (Cu) wires (e.g., >2 um thick) are currently fabricated with single damascene processing. The use of a single damascene process is mainly due to integration problems associated with dual-damascene processing, including the problem of contacting both MIM capacitors and underlying wiring layers during the via and wire etching processes. [0003] In the super thick dual-damascene Cu wire processes, the vias and trenches are defined using conventional lithography steps. In these conventional processes, the via is about 5.5. .mu.m in height and at about 1.5 .mu.m in width. After the formation of the via, the via is filled with spin on organic material such as, for example, anti-reflective coating (ARC), to the underlying Cu wiring layer Mx, for a trough lithographic step. [0004] However, it has been found that the second dual-damascene lithography step is difficult to make work in the super thick damascene Cu wire processes. By way of example, for a via first, trench last process, it has been found that the ARC forms an hourglass formation in the via which, in turn, results in large voids in the via. More specifically, it has been found that none of the industry standard mid UV (MUV) or Deep UV (DUV) ARCs achieved more than 40% fill, with all of them leaving large voids in the vias which opened up during trough etch. And, due to these voids, subsequent etching caused corrosion in an underlying metal layer due to the etchant etching through the voids. [0005] If the ARC, for example, is made thicker, there is better fill properties within the via; however, other problems arise during the subsequent etching process. For example, acceptable via fill can be achieved using an 0.8 um layer, but this severely complicates the trough RIE due to the very long ARC open step required, and due to large fences or rails generated around the vias during trough RIE. More specifically, during the RIE process using the thicker ARC fill, fences are formed on the sides of the via, early in the trough RIE process. This leads to preferential etching along the via edges down to an underlying metal (Mx) layer. Thus, it was found that when the ARC is of about 0.8 um, there is resist erosion, massive fencing and trough RIE (reactive ion etching) problems. [0006] The invention is directed to overcoming one or more of the problems as set forth above. SUMMARY OF THE INVENTION [0007] In a first aspect of the invention, a method comprises etching at least one partial via in a stacked structure and forming a border about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer. [0008] In embodiments, the performing step is part of a dual-damascene process. The forming of the border comprises forming a negative photoresist on the stacked structure and exposing portions of the negative photoresist remote from the at least one partial via. The at least one etch stop layer comprises a first etch stop layer over an Mx-1 metal layer and a second etch stop layer over a metal insulator metal (MIM) capacitor. The etch stop layer over the MIM capacitor is formed thicker than the etch stop layer over the Mx-1 metal layer. [0009] The method further includes incorporating a metal insulator metal (MIM) capacitor into the stacked structure and the thick wiring extends to the at least one etch stop layer over the MIM capacitor. The forming the stacked structure comprises providing a damascene copper wire formed in a first low K dielectric material and forming an etch stop layer on the first low K dielectric material. An interlevel dielectric layer and second dielectric layer is formed on the etch stop layer. A second etch stop layer is formed on the second low K dielectric layer, and a third low K dielectric layer is formed on the etch stop layer. [0010] The MIM capacitor comprises refractory metals or alloys comprising at least one W, WN, TiN, Ta, TaN and TiSiN. The at least one of the first and second low K dielectric material and the second dielectric layer is fluorine doped silicate glass (FSG). The etch stop layer and the second etch stop layer is at least silicon nitride, silicon carbo nitride, silicon oxy carbo nitride and silicon carbide. The MIM capacitor is embedded in the interlevel dielectric layer. The MIM capacitor is a plurality of plates with at least one of a silicon nitride, silicon carbo nitride, silicon oxy carbo nitride and silicon carbide etch stop layer. [0011] The etching the at least one partial via includes partially etching the stacked structure in alignment with at least one of an underlying metal layer and MIM capacitor. The performing step comprises depositing negative photoresist on the stacked structure after the formation of the at least one partial via, exposing the negative photoresist, remote from the at least one partial via to form a border, etching the at least one partial via further into the stacked structure and selectively etching to form at least one trough. The selective etching is selective to the at least one etch stop layer deposited on at least one of an underlying metal layer and MIM capacitor. [0012] In embodiments, the steps of the invention are used for fabrication of integrated circuit chips. The steps of the invention are a dual-damascene copper back end of line (BEOL) process, in which copper layers defined as a wire and via height have a thickness of about 3.5 microns or greater. The performing thick wiring using selective etching while continuing via etching to at least one etch stop layer includes a trough etch which extends to an upper embedded etch layer before the via extends to the at least one etch stop layer. [0013] In another aspect of the invention, the method is directed to making a dual-damascene copper BEOL structure. The method comprising forming a partial height via in alignment with at least an underlying metal layer and applying a negative photoresist material. The method further includes forming a border in the negative photoresist material proximate the partial height via and etching the partial height via to a further depth and selectively etching to form a trough. The method further includes incorporating a MIM capacitor into the BEOL structure. [0014] In embodiments, the etching step includes etching to at least an etch stop layer above a metal layer and the MIM capacitor. The method further comprises providing the underlying metal formed in a first low K dielectric material, forming an etch stop layer on the first low K dielectric material, forming an oxide layer and interlevel dielectric layer on the etch stop layer, embedding the MIM capacitor in the silicon dioxide layer, forming a cap layer on the MIM capacitor, forming a second etch stop layer on the interlevel dielectric layer, and forming a third low K dielectric layer on the etch stop layer. [0015] The etch stop layer and the second etch stop layer is at least one of a silicon nitride, silicon carbo nitride, silicon oxy carbo nitride and silicon carbide etch stop layer. The MIM capacitor is formed using a plurality of plates with at least one of a silicon nitride, silicon carbo nitride, silicon oxy carbo nitride and silicon carbide etch stop. The etching the partial height via to a further depth and selectively etching to form a trough includes etching the trough to an upper embedded etch layer before the via hits at least another etch stop layer. The forming of the border comprises exposing portions of the negative photoresist remote from the partial height via. The etching a trough comprises selectively etching to at least one of a cap layer over the MIM capacitor and an underlying metal layer. The etching the partial height via to a further depth and selectively etching to form a trough is in alignment with at least one of the underlying metal layer and the MIM capacitor. [0016] In another aspect of the invention, a dual-damascene method for fabricating a thick wire structure comprises forming a partial via in a stacked structure and depositing negative photoresist on the stacked structure after the formation of the partial via. The method further includes exposing the negative photoresist, remote from the partial via to form a border above the partial via. The partial via is etched further into the stacked structure. The method further includes selectively etching into the partial via to form a trough. The selective etching is selective to at least one etch stop layer deposited on at least one of an underlying metal layer. A MIM has at least an upper plate MIM dielectric and a lower plate. [0017] In embodiments, the thick wire structure has a thickness of about 3.5 microns or greater. The steps are designed for fabrication of integrated circuit chips. The MIM capacitor is formed by sputter clean removal of a MIM top plate of less than 10 nanometer oxide equivalent sputter removal such that the via is not fully etched through the upper plate and is not in contact with the MIM dielectric. The at least one etch stop is a first etch stop and a second etch stop. The first etch stop is formed over the underlying metal layer and the second etch stop is formed on a surface of the MIM capacitor and formed with a height greater than a height of the first etch stop. [0018] In another aspect of the invention, a thick wire structure comprises a damascene copper wire formed in a first dielectric layer and an etch stop layer covering the damascene copper wire. A second dielectric layer is formed on the etch stop layer. A second etch stop layer is formed on the second dielectric layer and a third dielectric layer is formed on the etch stop layer. A via approximately 1.5 microns or taller us formed through the first, second and third dielectric layer and contacts the damascene copper wire. A trough approximately 2 microns or taller is formed proximate to the second etch stop and in substantial axial alignment with the via and having a width larger than the via. A MIM capacitor is embedded in the oxide layer and an etch stop layer is formed over the MIM capacitor. The via is in alignment with and extends to the etch stop layer formed over the MIM capacitor and the trough is in axial alignment with the via formed over the MIM capacitor and stops near the second etch stop. A dielectric stack is approximately 5.5 um tall, with approximately 3.5 um tall wires and the via has a minimum width of approximately 1.2 um. [0019] In an aspect of the invention, a thick wire structure comprises an underlying wire formed in a FSG (fluorine doped silicate glass) dielectric material. A first nitride cap layer covers the underlying wire. An interlevel layer is formed on the first nitride cap layer. A MIM capacitor is embedded in a portion of the interlevel layer. A MIM etch stop cap layer is formed on the MIM capacitor, where the MIM cap layer has a thickness greater than the first nitride cap. A second nitride cap layer is formed on the interlevel layer. An FSG dielectric layer is formed on the second nitride cap. A via is in alignment with at least one of the underlying wire and the MIM capacitor, extending proximate to the MIM nitride cap layer and the first nitride cap layer. A trough is in substantial axial alignment with the via and having a width larger than the via and extending to the second nitride cap layer. In embodiments, the MIM capacitor is composed of refractory metals or alloys comprising at least one W, WN, TiN, Ta, TaN and TiSiN. BRIEF DESCRIPTION OF THE DRAWINGS [0020] FIG. 1 shows an initial structure in accordance with the invention; Continue reading about Dual-damascene process to fabricate thick wire structure... Full patent description for Dual-damascene process to fabricate thick wire structure Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Dual-damascene process to fabricate thick wire structure patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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