Dual clock spread for low clock emissions with recovery

This application is a continuation of co-pending U.S. patent application Ser. No. 12/111,572, filed Apr. 29, 2008, the entire disclosure of which is hereby incorporated herein by reference and to which the instant application claims priority.

The present invention relates to clock generation in general, and, in particular, to a method and apparatus for generating recovered clock signals with harmonic emission suppression.

Many electronic devices employ processors and/or other digital circuits that require clock signals for synchronization. Clock signals may be generated by a free-running oscillator driven by a crystal, an LC-tuned circuit, or an external clock source. Parameters of such clock signals may include maximum and minimum allowable clock frequencies, tolerances at high and low voltage levels, maximum rise and fall times on waveform edges, pulse-width tolerance for a non-square wave, and the timing relationship between clock phases if two-clock phase signals are needed.

High-speed electronic circuits are particularly susceptible to generating and radiating electromagnetic interference (EMI). Accordingly, many regulatory agencies, such as the Federal Communication Commission (FCC) and the Comite International Special Des Perturbations Radioelectriques (CISPR), have established maximum allowable EMI emission standards for electronic equipments, and promulgate guidelines concerning measurement equipment and techniques for determining EMI compliance.

The spectral components of the EMI emissions typically have peak amplitudes at harmonics of the fundamental frequency of a clock circuit. In order to comply with the above-mentioned governmental limits on EMI emissions, costly suppression measures or extensive shielding may need to be utilized. Other approaches for reducing EMI emissions include careful routing of signal traces on printed circuit boards to minimize loops and other potentially radiating structures. However, EMI emissions are made worse at higher clock speeds. Consequently, it would be desirable to provide an improved method and apparatus for generating high-speed clock signals having relatively low EMI emissions.

In accordance with embodiments consistent with the present invention, a method and apparatus provides for the generation and recovery of a stable clock signal having harmonic emission suppressions using a dual spread spectrum clock signals. The method comprises: generating first and second lower frequency dual clock signals from a high frequency clock signal, wherein said first and second lower frequency dual clock signals have respective frequencies that are less than a frequency of the high frequency clock signal; frequency modulating said first and second lower frequency dual clock signals to generate first and second modulated clock signals that sweep in opposing directions with respect to one another in a spectrum of operation; a receiver receiving said first and second modulated clock signals; the receiver generating a sum signal and a difference signal from said first and second modulated clock signals; the receiver filtering out the difference signal; and outputting the sum signal as a stable recovered clock signal of the receiver, said stable recovered clock signal having the frequency of the high frequency clock signal.