Driver circuit connected to pulse shaping circuitry

Title: Driver circuit connected to pulse shaping circuitry

Brief Patent Description - Full Patent Description - Patent Claims

The Patent Description & Claims data below is from USPTO Patent Application 20070222486, Driver circuit connected to pulse shaping circuitry.

1. A circuit, comprising: a first terminal coupled to a voltage source switchable between a first voltage level and a second voltage level; a driver comprising: a first inverter; a second inverter; an output stage comprising a PFET and an NFET having source drain paths connected in series across opposite power supply terminals, the PFET and NFET each having a gate electrode that switches on and off in response to a voltage applied to the gate electrode being on opposite sides of a threshold; first pulse shaping circuitry coupled to the first inverter and the PFET and comprising a first resistor and a first capacitor, the first capacitor being connected across the gate electrode of the PFET and a first of the power supply terminals, the first capacitor comprising an NFET; and second pulse shaping circuitry coupled to the second inverter and the NFET and comprising a second resistor and a second capacitor, the second resistor being connected the gate electrode of the NFET and a first of the power supply terminals, the first capacitor comprising an PFET.

2. The circuit of claim 1, wherein the first inverter comprises a PFET and an NFET having gate electrodes connected to be driven in parallel by the voltage at the first terminal and source drain paths which are switched on an off in a complementary manner in response to the voltage at the first terminal.

3. The circuit of claim 2, wherein the PFET of the first inverter comprises a source drain path coupled to a supply voltage and the NFET of the first inverter comprises a source drain path coupled to ground.

4. The circuit of claim 2, wherein the first resistor is connected between the source drain path of the NFET of the first inverter and the output terminal of the first inverter.

5. The circuit of claim 1, wherein the second inverter comprises a PFET and an NFET having gate electrodes connected to be driven in parallel by the voltage at the first terminal and source drain paths which are switched on an off in a complementary manner in response to the voltage at the first terminal.

6. The circuit of claim 5, wherein the PFET of the second inverter comprises a source drain path coupled to a supply voltage and the NFET of the first inverter comprises a source drain path coupled to ground.

7. The circuit of claim 5, wherein the first resistor is connected between the source drain path of the NFET of the first inverter and the output terminal of the first inverter.

8. The circuit of claim 1 wherein the first and second capacitors respectively include an NFET and a PFET.

9. The circuit of claim 1 wherein the voltage source cycles between a high voltage level and a ground voltage level.

10. The circuit of claim 9, wherein, in response to a transition of the voltage source between a ground level and a high voltage level, the PFET of the output stage is activated and the NFET of the output stage is deactivated.

11. The circuit of claim 10, wherein, in response to a transition of the voltage source between a ground level and a high voltage level, the first pulse shaping circuit introduces a delay in the activation of the PFET of the output stage.

12. The circuit of claim 9, wherein, in response to a transition of the voltage source between a high voltage level and a ground level, the NFET of the output stage is activated and the PFET of the output stage is deactivated.

13. The circuit of claim 10, wherein, in response to a transition of the voltage source between a high voltage level and a ground level, the second pulse shaping circuit introduces a delay in the activation of the NFET of the output stage.

14. A method of operating a driver circuit responsive to a source voltage that cycles between a high voltage level and a ground level, the driver circuit comprising a PFET and an NFET, each including a control electrode and a source path controlled in response to a voltage applied to the control electrode, the source drain paths of the first and second transistors being connected in series across opposite power supply terminals, and an output terminal between the series connected paths, the method comprising: during a transition of the voltage source between a ground level and a high voltage level, activating the PFET of the output stage and deactivating the NFET of the output stage, wherein activating the PFET of the output stage comprises delaying a threshold voltage value at the control electrode of the PFET; and during a transition of the voltage source between a high voltage level and a ground level, activating the NFET of the output stage and deactivating the PFET of the output stage, wherein activating the NFET of the output stage comprises delaying a threshold voltage value at the control electrode of the NFET.

15. The method of claim 14, wherein delaying a threshold voltage value at the control electrode of the PFET comprises charging a shunt capacitor coupled to the PFET.

16. The method of claim 15, further comprising discharging the shunt capacitor coupled to the PFET during a time period when the source voltage is at a ground voltage level.

17. The method of claim 14, wherein delaying a threshold voltage value at the control electrode of the NFET comprises charging a shunt capacitor coupled to the NFET.

18. The method of claim 17, further comprising discharging the shunt capacitor coupled to the NFET during a time period when the source voltage is at a high voltage level.

Brief Patent Description - Full Patent Description - Patent Claims

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Industry Class:
Miscellaneous active electrical nonlinear devices, circuits, and systems

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