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Driver circuit connected to pulse shaping circuitryDriver circuit connected to pulse shaping circuitry description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070222486, Driver circuit connected to pulse shaping circuitry. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATIONS [0001] This application is a continuation of commonly assigned and co-pending U.S. patent application Ser. No. 10/777,174, filed Feb. 13, 2004, which is a continuation of commonly assigned U.S. patent application Ser. No. 10/167,493, filed Jun. 13, 2002 the disclosures of which are incorporated by reference herein in their entirety. BACKGROUND [0002] The present invention relates generally to driver circuits and, more particularly, to a driver circuit including first and second opposite conductivity type transistors which are prevented from conducting simultaneously during a transition between first and second voltage levels by pulse shaping circuitry, and to a method of operating same. [0003] One type of driver circuit that is frequently employed, particularly on integrated circuit chips, includes first and second opposite conductivity type transistors, each including a control electrode and a path which is switched on and off between a pair of further electrodes. Each path is switched on and off in response to a voltage applied to the control electrode of the particular transistor being on opposite sides of a threshold. The paths of the first and second transistors are connected in series across terminals of a DC power supply. An output terminal between the series connected paths drives a load. [0004] In a typical integrated circuit chip, the transistors are opposite conductivity type metal oxide semiconductor field effect transistors (MOSFETs), wherein the control electrodes are gate electrodes and the further electrodes are source and drain electrodes. Such a driver includes a positive channel field effect transistor (PFET) and a negative channel field effect transistor (NFET). The switched path between the source and drain electrodes of each field effect transistor (FET) is frequently referred to as a source drain path and the source drain paths of the PFET and NFET are connected in series across opposite polarity terminals of the power supply. [0005] The typical integrated circuit chip includes many such drivers that are responsive to bilevel sources having positive and negative going transitions between first and second voltage levels that are usually approximately equal to the voltages at the power supply terminals. The bilevel sources can be either data or clock sources. In response to the bilevel source being at the first (low) voltage level, the PFET and NFET are respectively on and off, while the NFET and PFET are respectively on and off in response to the bilevel source being at the second (high) voltage level. A relatively high impedance is provided by the source drain path of the NFET or PFET which is off so that substantial current does not flow through both the PFET and NFET of the driver while the bilevel source is at the first and second voltage levels. To minimize power consumption, the PFET and NFET should not be on at the same time during the transitions. [0006] Many of the drivers of the foregoing type on a typical integrated circuit chip are simultaneously responsive to the transitions. If many of the drivers of the foregoing type are simultaneously responsive to the transitions and if the PFET and NFET of each of these drivers were on at the same time during the transitions, a substantial amount of current, frequently referred to as crow bar current, would be drawn from the power supply. The current could be so great as to cause overheating of the integrated circuit chip and result in a substantial decrease in the voltage between the power supply terminals. Similar problems can also exist with bipolar drivers including PNP and NPN transistors having series connected emitter collector paths. [0007] In the past, one approach to resolving the problem has involved complicated circuitry which takes into account processing variables in making the integrated circuits, as well as changes that occur to the circuit elements as a result of power supply voltage and temperature variations of the integrated circuit chip carrying the circuitry. Another complicated approach has involved staging a number of field effect transistors. These complicated circuits occupy a significant amount of space on the integrated circuit chip and consume additional power, resulting in possible unnecessary heating of the chip. [0008] There is a prior art circuit wherein conventional capacitors are connected in negative feedback paths to the gates of opposite conductivity type field effect transistors having series connected source drain paths. One electrode of each capacitor is connected to an output terminal between the source drain paths, while the other electrode of each capacitor is connected to the gate electrode of one of the field effect transistors. A problem with this approach is that the voltage across each of the capacitors varies as a function of load variations. Hence, switching of the field effect transistors is a function of the load variations which can result in poor control. In this prior art circuit, both field effect transistors appear to be turned on simultaneously during a transition, resulting in substantial current flow. Another problem with this prior art circuit is that the capacitors are charged and discharged through source drain paths of additional field effect transistors, rather than through resistors. BRIEF DESCRIPTION OF THE DRAWINGS [0009] FIG. 1 is a circuit diagram of a preferred embodiment of the present invention; and [0010] FIG. 2 includes a series of waveforms helpful in describing the operation of the circuit of FIG. 1. DETAILED DESCRIPTION [0011] Reference is now made to FIG. 1 of the drawing wherein driver circuit 10 is illustrated as being connected between bilevel voltage source 12 and load 14. Driver circuit 10, source 12 and load 14 are complementary metal oxide semiconductor (CMOS) circuits on an integrated circuit chip having a positive DC power supply terminal 16, at a potential of +1.0Vdd, and a negative DC power supply terminal 18, at ground potential, i.e., 0Vdd. The bilevel output of voltage source 12, which can be either a data or clock source, typically switches between potentials of 1.0Vdd and 0Vdd, and has positive and negative going short duration transitions between these potentials. Load 14, typically other circuitry on the integrated circuit and/or off chip circuitry, is subject to substantial variations, depending upon the number of circuits in load 14 which are activated at a particular time. [0012] Driver circuit 10 includes inverters 20 and 22, connected to be driven in parallel by the output of source 12. Driver circuit 10 also comprises output stage 24, including output terminal 26 which is connected in a DC circuit to drive load 14. Output stage 24 is connected to be responsive to output voltages of inverters 20 and 22 via DC circuits 28 and 30 which respectively include switched voltage controlled shunt capacitors 32 and 34. [0013] Inverter 20 includes complementary transistors in the form of PFET 36 and NFET 38 having gate electrodes connected to be driven in parallel by the bilevel output of source 12 at terminal 39 and source drain paths which are switched on and off in a complementary manner by the voltage applied to the gate electrodes of the PFET and NFET. The source drain paths of PFET 36 and NFET 38 are connected in series with each other and across DC power supply terminals 16 and 18. A resistive impedance, i.e., resistor 40, is connected in series with the source drain paths of PFET 36 and NFET 38, between the drains of the PFET and NFET of inverter 20. The use of resistor 40 as a resistive impedance, is advantageous because it (1) enables a lower resistance to be achieved and (2) provides better resistance value stability with regard to variations of integrated circuit temperature and power supply voltage, and integrated circuit manufacturing. A first end of DC circuit 28 is connected to a common terminal at one side of resistor 40 and the drain electrode of PFET 36. [0014] Inverter 22 is similar to inverter 20, in that inverter 22 includes PFET 42 and NFET 44 and a resistive impedance in the form of resistor 46. The gate electrodes of PFET 42 and NFET 44 are connected to be driven in parallel by the output voltage of source 12 at terminal 39 and the source drain paths of PFET 42 and NFET 44 are connected in series with each other and a resistive impedance, i.e., resistor 46. However, inverter 22 differs from inverter 20 because the common terminal of resistor 46 and the drain of NFET 44 are connected to a first end of DC circuit 30. Inverters 20 and 22 thus can be considered as switching circuits for selectively supplying, to the output terminals thereof, voltages substantially equal to the power supply voltages 1.0Vdd and 0Vdd. [0015] Output stage 24 includes PFET 48 and NFET 50 having source drain paths connected in series with each other across DC power supply terminals 16 and 18. The drain electrodes of PFET 48 and NFET 50 have a common connection to output terminal 26 which is connected to load 14. PFET 48 and NFET 50 have gate electrodes respectively connected to the second ends of DC circuits 28 and 30. The gate electrodes of PFET 48 and NFET 50 are respectively connected to first electrodes of shunt capacitors 32 and 34. The second electrode of capacitor 32 is connected to ground DC power supply terminal 18, while the second electrode of capacitor 34 is connected to +Vdd power supply terminal 16. Because of the connections of the electrodes of capacitors 32 and 34 to the gate electrodes of PFET 48 and NFET 50 and to the constant voltages at the power supply terminals 16 and 18, the waveforms across the capacitors are independent of the current that load 14 draws from output stage 24. PFET 48 and NFET 50 have thresholds such that (1) in response to the voltage applied to the gate electrode of PFET 48 being less than and greater than the threshold voltage of the PFET, the PFET source drain path is turned on and off, respectively, and (2) in response to the voltage applied to the gate electrode of NFET 48 being less than and greater than the threshold voltage of the NFET, the NFET source drain path is turned off and on, respectively. [0016] In the preferred embodiment, capacitors 32 and 34 respectively comprise NFET 52 and PFET 54. One electrode of each of capacitors 32 and 34 respectively comprises the gate electrodes of NFET 52 and PFET 54. The other electrode of each of capacitors 32 and 34 respectively comprises the source drain paths of NFET 52 and PFET 54. The source and drain electrodes of NFET 52 are connected together and to ground terminal 18, while the source and drain paths of PFET 54 are connected together and to +Vdd power supply terminal 16. Each of NFET 52 and PFET 54 includes an insulator between the gate electrode and the source drain path thereof. [0017] The circuitry of FIG. 1, including the thresholds of PFET 48 and NFET 50, is such that the source drain paths of PFET 48 and NFET 50 are never simultaneously on. Consequently, crowbar current cannot flow between power supply terminals 16 and 18 through the source drain paths of PFET 48 and NFET 50. [0018] Reference is now made to FIG. 2 of the drawing which is helpful in describing the operation of the circuit of FIG. 1. The output voltage of source 12, indicated by bilevel waveform 60, is illustrated as having a 50-50 duty cycle, although it is to be understood that the output of source 12 can have any suitable duty cycle for a clock or data source. [0019] During the half cycles of source 12 when the output voltage of the source has a value of 1.0Vdd, NFETs 38 and 44 are turned on and PFETs 36 and 42 are turned off. Consequently, a voltage approximately equal to the ground voltage at terminal 18 is supplied to the first end of DC circuit 28 (at the drain of PFET 36) through the low impedance, turned on source drain path of PFET 38 and resistor 40. At the same time, the ground voltage at terminal 18 is supplied to the first, input end of DC circuit 30 (at the drain of NFET 44) through the low impedance, turned on source drain path of NFET 44. Just before the end of the half cycles when the output voltage of source 12 has a value of 1.0Vdd, inverters 20 and 22 apply low voltages, substantially equal to the voltage at ground terminal 18, to the gate electrodes of PFET 48 and NFET 50, causing the PFET and-NFET to be respectively turned on and off. In addition, at this time there is virtually no voltage across the insulator of NFET 52 because the gate electrode thereof and the source drain path thereof are both substantially at ground potential, resulting in the voltage across capacitor 32 being zero. In contrast, because (1) NFET 44 is turned on, causing the input of DC path 30 to be substantially at ground, i.e., 0Vdd, and (2) the source drain path of PFET 54 is at 1.0Vdd, there is a voltage substantially equal to 1.0Vdd across the insulator of PFET 54 that comprises capacitor 34. [0020] During the half cycles of source 12 when the output voltage of the source has a value of 0Vdd, NFETs 38 and 44 are turned off and PFETs 36 and 42 are turned on. Consequently, the 1.0Vdd voltage at terminal 16 is supplied to the first, input end of DC circuit 28 (at the drain of PFET 36) through the low impedance, turned on source drain path of PFET 36. At the same time, the 1.0Vdd voltage at terminal 16 is supplied to the first end of DC circuit 30 (at the drain of NFET 44) through resistor 46 and the low impedance, turned on source drain path of PFET 42. Just before the end of the half cycles when the output voltage of source 12 has a value of 0Vdd, inverters 20 and 22 apply high voltages, substantially equal to the 1.0Vdd voltage at power supply terminal 16, to the gate electrodes of PFET 48 and NFET 50, causing the PFET and NFET to be respectively turned off and on. Also, at this time there is virtually no voltage across the insulator of PFET 54 because the gate electrode thereof and the source drain path thereof are both substantially at 1.0Vdd, resulting in the voltage across capacitor 34 being zero. In contrast, because (1) PFET 36 is turned on, causing the input of DC path 28 to be substantially at 1.0Vdd, and (2) the source drain path of NFET 52 is at ground potential, there is a voltage substantially equal to 1.0Vdd across the insulator of NFET 52, which has a finite capacitance value. Continue reading about Driver circuit connected to pulse shaping circuitry... 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