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Double gate strained-semiconductor-on-insulator device structuresRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode)Double gate strained-semiconductor-on-insulator device structures description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060197124, Double gate strained-semiconductor-on-insulator device structures. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATIONS [0001] This application claims the benefit of U.S. Provisional Application 60/386,968 filed Jun. 7, 2002, U.S. Provisional Application 60/404,058 filed Aug. 15, 2002, and U.S. Provisional Application 60/416,000 filed Oct. 4, 2002; the entire disclosures of these three provisional applications are hereby incorporated by reference. FIELD OF THE INVENTION [0002] This invention relates to devices and structures comprising strained semiconductor layers and insulator layers. BACKGROUND [0003] Strained silicon-on-insulator structures for semiconductor devices combine the benefits of two advanced approaches to performance enhancement: silicon-on-insulator (SOI) technology and strained silicon (Si) technology. The strained silicon-on-insulator configuration offers various advantages associated with the insulating substrate, such as reduced parasitic capacitances and improved isolation. Strained Si provides improved carrier mobilities. Devices such as strained Si metal-oxide-semiconductor field-effect transistors (MOSFETs) combine enhanced carrier mobilities with the advantages of insulating substrates. [0004] Strained-silicon-on-insulator substrates are typically fabricated as follows. First, a relaxed silicon-germanium (SiGe) layer is formed on an insulator by one of several techniques such as separation by implantation of oxygen (SIMOX), wafer bonding and etch back; wafer bonding and hydrogen exfoliation layer transfer; or recrystallization of amorphous material. Then, a strained Si layer is epitaxially grown to form a strained-silicon-on-insulator structure, with strained Si disposed over SiGe. The relaxed-SiGe-on-insulator layer serves as the template for inducing strain in the Si layer. This induced strain is typically greater than 10.sup.-3. [0005] This structure has limitations. It is not conducive to the production of fully-depleted strained-semiconductor-on-insulator devices in which the layer over the insulating material must be thin enough [<300 angstroms (.ANG.)] to allow for full depletion of the layer during device operation. Fully depleted transistors may be the favored version of SOI for MOSFET technologies beyond the 90 nm technology node. The relaxed SiGe layer adds to the total thickness of this layer and thus makes it difficult to achieve the thicknesses required for fully depleted silicon-on-insulator device fabrication. The relaxed SiGe layer is not required if a strained Si layer can be produced directly on the insulating material. Thus, there is a need for a method to produce strained silicon--or other semiconductor--layers directly on insulating substrates. Double-gate MOSFETs [0006] Double gate MOSFETs have the potential for superior performance in comparison to standard single-gate bulk or single-gate SOI MOSFET devices. This is due to the fact that two gates (one above and one below the channel) allow much greater control of channel charge then a single gate. This configuration has the potential to translate to higher drive current and lower stand-by leakage current. finFETs [0007] Fin-field-effect transistors (finFETs), like double-gate MOSFETs, typically have two gates (one on either side of the channel, where the channel is here oriented vertically) allowing much greater control of channel charge than in a single gate device. This configuration also has the potential to translate to higher drive current and lower stand-by leakage current. Devices related to the finFET, such as the wrap-around gate FET (gate on both sides of as well as above the channel) allow even more channel charge control and hence even more potential for improved drive current and leakage current performance. Bipolar-CMOS [0008] The bipolar-CMOS (BiCMOS) process is a combination of both the bipolar transistor and MOSFET/CMOS processes. Individually, the CMOS process allows low power dissipation, high packing density and the ability to integrate complexity with high-speed yields. A major contribution to power dissipation in CMOS circuits originates from driving the load capacitance that is usually the gate of sequentially linked logic cells. The size of these gates may be kept sufficiently small, but when driving higher loads (such as input/output buffers or data buses) the load or capacitance of such devices is substantially larger and therefore requires greater gate width (hence area) of transistor, which inevitably drives down the switching speed of the MOSFET. [0009] The bipolar transistor has significant advantages in terms of the drive current per unit active area and reduced noise signal. Additionally, the switching speed is enhanced due to the effectively exponential output current swing with respect to input signal. This means that the transconductance of a bipolar transistor is significantly higher than that of a MOS transistor when the same current is passed. Higher transconductance enables the charging process to take place approximately ten times more quickly in emitter coupled logic circuits, or high fan out/load capacitance. [0010] Pure bipolar technology has not replaced the high packing density microprocessor CMOS process for a number of reasons, including issues of yield and the increased area required for device isolation. However, integration of bipolar and CMOS may provide the best aspects of the composite devices. [0011] The advantages of BiCMOS process may be summarized as follows: [0012] 1. Improved speed performance of highly integrated functionality of CMOS technology; [0013] 2. Lower power dissipation than bipolar technology; [0014] 3. Lower sensitivity to fan out and capacitive load; [0015] 4. Increased flexibility of input/output interface; [0016] 5. Reduced clock skew; [0017] 6. Improved internal gate delay; and [0018] 7. Reduced need for aggressive scaling because a 1-2 .mu.m BiCMOS process offers circuit speed equivalent to that of sub-micron CMOS. SUMMARY [0019] The present invention includes a strained-semiconductor-on-insulator (SSOI) substrate structure and methods for fabricating the substrate structure. MOSFETs fabricated on this substrate will have the benefits of SOI MOSFETs as well as the benefits of strained Si mobility enhancement. For example, the formation of BiCMOS structures on SSOI substrates provides the combined benefits of BiCMOS design platforms and enhanced carrier mobilities. SSOI substrates also enable enhanced carrier mobilities, process simplicity, and better device isolation for double-gate MOSFETs and finFETs. [0020] By eliminating the SiGe relaxed layer traditionally found beneath the strained Si layer, the use of SSOI technology is simplified. For example, issues such as the diffusion of Ge into the strained Si layer during high temperature processes are avoided. [0021] This approach enables the fabrication of well-controlled, epitaxially-defined, thin strained semiconductor layers directly on an insulator layer. Tensile strain levels of .about.10.sup.-3 or greater are possible in these structures, and are not diminished after thermal anneal cycles. In some embodiments, the strain-inducing relaxed layer is not present in the final structure, eliminating some of the key problems inherent to current strained Si-on-insulator solutions. This fabrication process is suitable for the production of enhanced-mobility substrates applicable to partially or fully depleted SSOI technology. [0022] In an aspect, the invention features a structure including a substrate having a dielectric layer disposed thereon and a fin-field-effect transistor disposed over the substrate. The fin-field-effect-transistor includes a source region and a drain region disposed in contact with the dielectric layer, the source and the drain regions includinga strained semiconductor material. The fin-field-effect-transistor also includes at least one fin extending between the source and the drain regions, the fin including a strained semiconductor material. A gate is disposed above the strained semiconductor layer, extending over at least one fin and between the source and the drain regions. A gate dielectric layer is disposed between the gate and the fin. [0023] One or more of the following features may be included. The fin may include at least one of a group II, a group III, a group IV, a group V, of a group VI element. The strained semiconductor layer may be tensilely strained and may include, e.g., tensilely strained silicon. The strained semiconductor layer may be compressively strained and may include, e.g., compressively strained germanium. [0024] In another aspect, the invention features a method for forming a structure, the method including providing a substrate having a dielectric layer disposed thereon, and a first strained semiconductor layer disposed in contact with the dielectric layer. A fin-field-effect transistor is formed on the substrate by patterning the first strained semiconductor layer to define a source region, a drain region, and at least one fin disposed between the source and the drain regions. A dielectric layer is formed, at least a portion of the dielectric layer being disposed over the fin, and a gate is formed over the dielectric layer portion disposed over the fin. [0025] One or more of the following features may be included. The first strained semiconductor layer may include at least one of a group II, a group III, a group IV, a group V, or a group VI element. The strained semiconductor layer may be tensilely strained and may include, e.g., tensilely strained silicon. The strained semiconductor layer may be compressively strained and may include, e.g., compressively strained germanium. Continue reading about Double gate strained-semiconductor-on-insulator device structures... Full patent description for Double gate strained-semiconductor-on-insulator device structures Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Double gate strained-semiconductor-on-insulator device structures patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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