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  Display module, drive method of display panel and display deviceUSPTO Application #: 20060017663Title: Display module, drive method of display panel and display device Abstract: A display device includes a display panel in which column direction wirings 15 and row direction wirings 16 are formed perpendicularly to each other and the column direction wirings 15 are divided into N sets (N is an integer of 2 or more) in the vertical direction of a screen, drive elements 13, 18 which drive each of these N sets of the column direction wirings 15, a scanning element 14 which scans the row direction wirings 16, and an interpolation element 19 which performs flame-interpolation on an input video signal N times; wherein the scanning element 14 simultaneously scans the row direction wirings 16 corresponding to these N sets of the column direction wirings 15 respectively with approximately 1/N the vertical cycle of the video signal, and the drive elements 13, 18, to which an interpolated video signal from the interpolation element 19 is input, drive each of these N sets of the column direction wirings 15 by the interpolated video signal with a frame shifted by 1/N the vertical cycle of the input video signal. A flat display panel such as an FED panel is provided in which high display luminance is obtained with high picture quality and a simple wiring structure. (end of abstract) Agent: Frommer Lawrence & Haug LLP - New York, NY, US Inventors: Yosuke Yamamoto, Hisafumi Motoe, Satoshi Miura, Takeya Meguro USPTO Applicaton #: 20060017663 - Class: 345075200 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20060017663. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCES TO RELATED APPLICATIONS [0001] The present invention contains subject matter related to Japanese Patent Application JP 2004-157937 filed in the Japanese Patent Office on May 27, 2004, the entire contents of which being incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a display module, a drive method of a display panel and a display device, and particularly to the ones suitably applied to an FED display device in which a field emission type cathode is used and to an organic electroluminescence display device or the like. [0004] 2. Description of the Related Art [0005] Recently, as one of flat panel type displays used for a display device, for example, a display device in which a field emission type cathode is used is developed. As the display device in which the field emission type cathode is used, there is what is called a field emission display (hereinafter called an FED). [0006] In the FED are obtained a number of characteristics such as a high grayscale display with the angle of view secured, high picture quality and production efficiency, high response speed, operation in the environment of very low temperature, high luminance, and high power efficiency. Further, the production process of an FED is simplified in comparison with that of an active matrix type liquid crystal display, and it is expected that the production cost be 40% to 60% lower than the active matrix type liquid crystal display. [0007] FIG. 1 shows an example of a structure of an FED panel. In the FED panel, a cathode panel 35 and an anode panel 37 are faced with a gap in vacuum condition in between. The cathode panel 35 is formed such that a plurality of cathode electrodes 39 and a plurality of gate electrodes 311 are formed on a support body 313 perpendicularly to each other with an insulation layer 38 in between, and an electron emission region 312 is formed at each intersection of the cathode electrode 39 and the gate electrode 311. [0008] On the other hand, the anode panel 37 is formed such that phosphor layers 31, 32 and 33 corresponding to R (red), G (green) and B (blue) of three primary colors of light are applied to a substrate 30 made of a transparent material and an anode electrode 36 made of a transparent material is formed to be a layer on the phosphor layers 31, 32 and 33. In this example, a black matrix 34 is formed between the phosphor layers 31, 32, 33 and the anode electrode 36. [0009] FIG. 2 is a sectional view showing the inside structure of the electron emission region 312. A cathode electrode 21 (corresponding to the cathode electrode 39 in FIG. 1) is formed on a glass 25 (corresponding to the substrate 30 in FIG. 1); a gate electrode 20 (corresponding to the gate electrode 311 in FIG. 1) is formed on the cathode electrode 21 with a resistance 24 and an insulation layer 211 (corresponding to the insulation layer 38 in FIG. 1) in between. A plurality of openings that are shown as openings 310 in FIG. 1 are provided on the insulation layer 211 and gate electrode 20, and a cathode element (cold cathode) 22 corresponding to each opening is formed on the cathode electrode 21 to strengthen an electric field (only one opening and one cathode element 22 are illustrated in FIG. 2). The cathode element and cathode electrode are electrically connected. In other words, the field emission type cathode is formed of the cathode electrode 21 and the plurality of cathode elements 22. [0010] As shown in FIG. 1, each electron emission region 312 is faced to one of the phosphor layers 31, 32 and 33 of the anode electrode 36, and three adjacent electron emission regions 312 respectively facing the phosphor layers 31, 32 and 33 correspond to one pixel. [0011] Therefore, by applying voltage between the gate electrode 311 and the cathode electrode 39 of the electron emission region 312, electrons are emitted from the cathode elements 22 (FIG. 2) of the electron emission region 312, and by applying voltage between the anode electrode 36 of the anode panel 37 and the cathode electrode 39 of the electron emission region 312, the above electrons emitted are attracted to the side of the anode electrode 36, and these electrons collide with the phosphor layers 31, 32 and 33, whereby light is emitted from the phosphor layers 31, 32 and 33. [0012] Next, the drive principle of a field emission type cathode used for the FED mentioned above is explained. In FIG. 2, by applying voltage Vcol to the cathode electrode 21 from a variable voltage source 210 and by applying voltage Vrow to the gate electrode 20 from a variable voltage source 29, and accordingly when the voltage difference expressed as Vgc is applied between the cathode electrode 21 and gate electrode 20, electrons are emitted from the cathode elements 22 by an electric field generated with the applied voltage. At this time, if voltage HV is applied to the anode electrode 27, electrons are attracted to the anode electrode 27 under the condition of HV>Vrow (1) and thereby anode current Ia flows to the cathode electrode 21 from the anode electrode 27 of FIG. 2. At this time, upon applying phosphors 26 (corresponding to phosphor layers 31, 32, and 33 in FIG. 1) to the anode electrode 27, the phosphors 26 emit light by energy of the above described electrons. [0013] If voltage Vgc is changed, the amount of electrons emitted from the cathode elements 22 is changed, whereby anode current Ia is also changed. Further, the amount of light emitted from the phosphors 26, that is, light emission luminance L is proportional to anode current Ia and is expressed as follows. L.varies.Ia (2) [0014] Therefore, if the above voltage described Vgc is changed, the emitted light luminance L can be changed. Accordingly, the luminance can be modulated by modulating the voltage Vgc in accordance with the signal to be displayed. [0015] FIG. 3 shows an example of a basic structure of an FED display system in which the above described FED panel is used. A support body 17 is a support body (corresponding to the support body 313 in FIG. 1) constituting a cathode panel of the FED panel. On the support body 17, a plurality of column direction wirings 15 and a plurality of row direction wirings 16 are formed, and gate electrodes, cathode electrodes and electron emission regions as shown in FIG. 1 exist at each intersection of the column direction wirings 15 and the row direction wirings 16 (although not shown in the figure, an anode panel is faced above the cathode panel as shown in FIG. 1). [0016] An FED module is formed by connecting a column direction pixel drive voltage generator 13 and row direction drive pixel selecting voltage generator 14 to the column direction wirings 15 and row direction wirings 16 of this FED panel, respectively. [0017] Further, the FED display system shown in FIG. 3 is an example in which an input video is of an analogue signal, and includes an A/D converter 10 that converts the analogue signal input to this FED panel display system into a digital signal, a video signal processor 11 to which the digital video signal from the A/D converter 10 is input and a control signal generator 12. [0018] The row direction drive pixel selecting voltage generator 14 is provided to selectively apply a variable row direction selection voltage Vrow (refer to FIG. 2) to the row direction wirings 16 and, for example, 35V is applied when selected and 0V is applied when not selected. [0019] The column direction pixel drive voltage generator 13 mainly includes, though not shown in the figure, a shift register for inputting the digital video signals (typically digital signals of R (Red), G (Green) and B (blue)) of one line (=one horizontal period), a line memory for retaining the above described digital video of one line period, a D/A converter in which the above one line video is converted into analogue voltage to be applied for one line period, and the like; and applies a variable column direction drive voltage Vcol (refer to FIG. 2) to the column direction wirings 15 simultaneously by one line. [0020] For example, when the row direction selection voltage Vrow is selected, namely when 35V is applied, if the column direction drive voltage Vcol is 0V, the voltage difference between the gate and cathode becomes 35V, and the amount of electrons emitted from the cathode element 22 (refer to FIG. 2) increases, and the light emitted from the phosphors 26 (refer to FIG. 2) becomes high luminance. Further, similarly, when the row direction selection voltage Vrow is selected, namely when 35V is applied and if the column direction drive voltage Vcol is 15V, the voltage difference Vgc between the gate and cathode becomes 20V; however, because the electron emitted has the characteristic of emission as shown in FIG. 12 with respect to Vgc, electrons are not emitted when the Vgc is 20 v, consequently no light is emitted. Therefore, display with the desirable luminance can be performed by controlling the column direction drive voltage Vcol from 0V through 15V in accordance with the input video signal level. [0021] In the case where a picture is displayed on the FED panel, the row direction wirings 16 are sequentially driven (scanned) by one line and synchronously, modulated signals of the picture of one line are applied to the column direction wirings 15 simultaneously, thereby controlling the irradiation amount of electron beams to the phosphors and displaying the picture by the line sequence. [0022] The video signal processor 11 applies picture quality adjustment processing and matrix processing to the digital video signal from the A/D converter 10, outputs a digital signal of each 8-bit R, G and B, for example, and outputs a horizontal synchronous signal and vertical synchronous signal. The digital signal of R, G and B of is directly input to the column direction pixel drive voltage generator 13. Further, the horizontal synchronous signal and vertical synchronous signal are input to the control signal generator 12. Continue reading... Full patent description for Display module, drive method of display panel and display device Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Display module, drive method of display panel and display device patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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