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  Display device, display driver, and data transfer methodUSPTO Application #: 20060017715Title: Display device, display driver, and data transfer method Abstract: A display device includes a display unit and a plurality of display drivers. Each of the display drivers has a digital operation unit and a drive unit. The digital operation unit of each display driver has a signal determination unit for determining whether or not a destination of an input signal is a display driver which is currently receiving the input signal, based on an ID signal contained in the input signal. The display driver fetches a display data signal contained in the input signal if the signal determination unit determines that the destination of the input signal is the display driver concerned. (end of abstract) Agent: Drinker Biddle & Reath (dc) - Washington, DC, US Inventors: Tohru Kimura, Hideaki Watanabe USPTO Applicaton #: 20060017715 - Class: 345204000 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20060017715. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a display device, a display driver, and a data transfer method. [0003] 2. Description of the Related Art [0004] Data driver IC are used in industrial fields of flat displays. Video signals processed by using ultra-large-scale integration circuits are supplied to such data driver IC. The data driver IC are configured to convert the input video signals into signals for driving a display panel. [0005] An example of a data driver for a color plasma display panel (PDP) used in a color PDP module is described in a document titled "MOS Integrated Circuit .mu.PD16373, 256/192 Bit Switching, AC-PDP driver, NEC Corporation., March, 2001." [0006] Referring to FIG. 7 of the accompanying drawings, the configuration of a conventional wide XGA (W-XGA; 1365.times.768 pixels) color PDP module 4 that uses the data driver described in the above-mentioned document titled "MOS Integrated Circuit .mu.PD16373, 256/192 Bit Switching, AC-PDP driver, NEC Corporation., March, 2001," is now described. This data driver has a 256-bit output and 4-phase input. [0007] As shown in FIG. 7, the conventional color PDP module 4 receives an input video signal 5 from outside, and applies video signal processing operations on the input video signal 5 using a low-voltage signal with a voltage of 3.3 V or less in an ultra-large-scale integration circuit on a digital signal processing board 1. Then, the signals are sent to a data driver 2 after raising the signal voltage to 5.0 V at the output stage of the digital signal processing board 1, in order to drive a PDP 50. [0008] The data driver 2 simultaneously outputs the data of one line (1365 pixels) to the plasma display panel. For this purpose, the W-XGA display panel requires sixteen (1365.times.3 [1 pixel for each RGB]/256=<16) 256-bit output data drivers 2. [0009] Each data driver 2 has six signal lines: four lines for video input signals (Data), one line for clock input signal (CLK), and one line for latch enable input signal (LE). Therefore, the number of signal lines 3 extending from the digital signal processing board 1 to the data driver 2 becomes 96 (6.times.16=96). [0010] The data driver 2 includes a register, a level conversion circuit for voltage conversion (amplification) and a high-voltage output buffer. [0011] A video data signal transferred from the digital signal processing board 1 in synchronization with a transfer clock signal is introduced in the data driver 2. The video data signal is stored in the register of the data driver 2 and sent to the level conversion circuit in synchronization with the input of the latch enable signal. [0012] All the signals supplied into the data driver 2 have an amplitude of 5.0 V. In the data driver 2, the section (including the register) up to the input to the level conversion circuit is a low-voltage operation unit 21. In the low-voltage operation unit 21, processing is conducted at an amplitude of 5.0 V. The level conversion circuit is a voltage conversion unit 22, and the signal with an amplitude of 5.0 V is amplified to an amplitude of 70 V. In the data driver 2, the section including and following the level conversion circuit (including the high-voltage output buffer) is a high-voltage operation unit 23. The high-voltage signal generated from the level conversion circuit is supplied to the PDP via the high-voltage output buffer. [0013] The following problems are associated with the above-described data transfer method. [0014] The first problem is that the phase difference between a total of 96 video data signals, clock signals, and latch enable signals cannot be stored. [0015] For example, if the phase of the video data signal is different from the phase of the clock signal, the video signal set in the register of the data driver 2 becomes one signal before or one signal after the intended signal. In this case, the display position of the pixels is shifted and abnormal image is displayed. This problem rises because of the necessity to transfer a large number of high-speed signals over a long distance. [0016] In order to explain this problem, a color PDP with a scanning period of 1 .mu.s (microsecond) will be described below. [0017] A fact that a scanning period of a color PDP is 1 .mu.s means that the interval in which a data driver outputs a video signal of one line to the plasma display panel is 1 .mu.s. Video data of the first line are sent to the plasma display panel, then after 1 .mu.s, the video data of the second line is sent to the plasma display panel, and then after 1 .mu.s, the video data of the third line is sent to the plasma display panel. The data driver updates the data every 1 .mu.s. For example, a 256-bit, 4-layer input data driver requires 64 transfer clocks to fetch the data of one line (this is because 256/4=64). In order to fetch data of 64 clocks within an interval of 1 .mu.s, the interval of 1 clock has to be 15.6 ns (nanosecond) or less, and a clock frequency has to be 64 MHz. [0018] A plasma display panel is a flat panel with a large surface area, and 50-inch display panels have a width of about 1 m 20 cm and a height of about 70 cm. Therefore, a total of 96 high-speed signals have to be sent with a phase difference of a nanosecond order to data drivers with a wiring length difference of about 1 m. This is very difficult to implement with the present semiconductor technology. [0019] Also, the interfaces between the digital board data drivers is the main cause of a high cost and a small reliability margin. [0020] Thus, a large number of pins of the signal processing LSI on the digital signal processing board 1, a large number of signal output buffers on the digital signal processing board 1, and a large number of wiring from the digital signal processing board 1 to the data drivers 2 are required (89 wiring for a W-XGA module) and the cost is high. The system has a large surface area, high power consumption, and a wide operation temperature range, so that noise penetration occurs from the high-voltage operation unit via a power source and GND and skew occurs between the data signals and between the data signal and clock signal due to a multipin configuration. Consequently, it is in principle difficult to guarantee the setup/hold in the data driver input unit, and ensure a satisfactory operation reliability margin. [0021] The second problem is that signals are not correctly introduced into a low-voltage input unit. Like the first problem, the unintended signals are supplied into the data driver 2, thereby producing a display video abnormality. This problem rises due to the occurrence of a bounce at a power source potential and ground potential when a large current flows in a high-voltage operation unit. The operation voltage of the high-voltage operation unit is 70 V, and the operation voltage of the low-voltage operation unit is 5.0 V. There is only one ground potential in a color PDP module. If the ground potential bounces at about 2 V as the high-voltage operation unit operates, the input threshold of the low-voltage operation unit fluctuates through 2 V and becomes close to a logical threshold (2.5 V). As a result, the input signal with a high potential to low potential ratio (H/L) with a signal amplitude of only 5 V is not appropriately fetched to the register. SUMMARY OF THE INVENTION [0022] One object of the present invention is to provide a display device that enables highly reliable and low-cost signal input. Continue reading... Full patent description for Display device, display driver, and data transfer method Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Display device, display driver, and data transfer method patent application. Patent Applications in related categories: 20080106533 - Apparatus for providing multiple screens and method of dynamically configuring multiple screens - An apparatus for providing multiple screens and a method of dynamically configuring multiple screens are provided. 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