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  Digital-to-analog converter and method thereofUSPTO Application #: 20080036635Title: Digital-to-analog converter and method thereof Abstract: A digitally controlled analog circuit comprises a finite state machine configured for receiving a digital input word and generating at least two digital codes in a manner determined by a state of the finite state machine. The digital codes are decoded into respective sets of binary data. The sets of binary data control respective switched-circuit arrays to generate an analog output corresponding to the digital input word. To establish a monotonic function between the digital input word and the analog output during steady state operations, the finite state machine switches states when a wrap-around condition is detected for one of the digital codes. The finite state machine uses different sets of equations in different states to derive the digital codes. (end of abstract)
Agent: Knobbe Martens Olson & Bear LLP - Irvine, CA, US Inventor: Chia-Liang Lin USPTO Applicaton #: 20080036635 - Class: 341144 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20080036635. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001]The present application claims priority benefits under 35 U.S.C. .sctn. 119(e) from U.S. Provisional Application No. 60/822,078, filed on Aug. 11, 2006, entitled "Digital-to-Analog Converter and Method Thereof," which is hereby incorporated herein in its entirety by reference. BACKGROUND OF THE INVENTION [0002]1. Field of the Invention [0003]The present invention relates to a digital-to-analog converter and in particular to a method and apparatus for improving monotonicity in a digital-to-analog converter. [0004]2. Description of the Related Art [0005]A digital-to-analog converter (DAC) is an important device for many applications. A DAC is an analog circuit whose output characteristics are controlled by a digital control word. While the present invention is generally related to a DAC and can be practiced in a general-purpose DAC, it is particularly useful for a special application of a digitally controlled oscillator (DCO). [0006]A DCO is a device that generates a periodic signal having a frequency controlled by a digital control word. A DCO usually comprises an adjustable circuit element whose value determines the oscillation frequency of the DCO. The digital control word is used to set the value of the adjustable circuit element and to determine the oscillation frequency. For example, an LC oscillator with an oscillation frequency of approximately f osc = 1 2 .pi. LC can be implemented as a DCO with a fixed inductor L and a variable capacitor C. The capacitance value of the variable capacitor is controlled by a digital control word. The DCO is a special case of a DAC since it receives a digital control word and outputs an analog signal in response to the digital control word. [0007]FIG. 1 depicts a typical digitally controlled variable capacitor 100 comprising a decoder 110, a fixed capacitor CF, a plurality of switched capacitors (e.g., C0, C1, C2) and a plurality of switches (e.g., S0, S1, S2). The decoder 110 receives a digital control word W and generates a plurality of binary data (e.g., D[0], D[1], D[2]) to respectively control the plurality of switches. The total effective capacitance of the variable capacitor 100 is C.sub.eff=CF+C0D[0]+C1D[1]+C2D[2]+ . . . . Thus, the oscillation frequency of an LC oscillator comprising the variable capacitor 100 is determined by the digital control word W. [0008]There are three important characteristics concerning a DCO: range, resolution, and monotonicity. The range and the granularity of the values of the adjustable circuit element respectively determine the range and the resolution of the DCO. For example, the resolution of the aforementioned LC oscillator is determined by the minimum capacitance among the switched capacitors (e.g., C0, C1, C2) while the range is determined by the maximum total effective capacitance (e.g., C.sub.eff (max)=CF+C0+C1+C2+ . . . ) and the minimum total effective capacitance (e.g., C.sub.eff (min)=CF). The monotonicity of the DCO is met if the value of the adjustable circuit element changes consistently (e.g., increases or decreases as the digital control word increases or decreases). For example, the monotonicity of the above mentioned LC oscillator is met if a greater control word results in a greater total effective capacitance. [0009]A DCO is usually incorporated in a digital phase lock loop (DPLL) to generate an output clock of a target frequency. A digital control word for the DCO is established in a closed-loop manner to control the oscillation frequency of the DCO. The digital control word has a limited resolution and so the instantaneous oscillation frequency of DCO also has a limited resolution. In practice, the instantaneous oscillation frequency of the DCO is unlikely to be exactly the same as the target frequency. A prior art DPLL usually requires a strictly monotonic DCO to ensure stable operations. For example, in an application in which a greater digital control word corresponds to a greater output frequency, the DPLL will seek to decrease the digital control word to decrease an output frequency that is higher than the target frequency or increase the digital control word to increase an output frequency that is lower than the target frequency. In a steady state of a stable DPLL, the digital control word usually fluctuates between two values, one corresponding to an output frequency slightly higher than the target frequency and another corresponding to an output frequency slightly lower than the target frequency such that an average output frequency is approximately equal to the target frequency. [0010]Fluctuations in the digital control word results in unwanted jitters in the output clock. The jitters can be reduced by increasing the resolution of the DCO such that the instantaneous oscillation frequency can be closer to the target frequency. A DPLL, however, is subject to disturbance due to noise and the digital control word may momentarily drift away from its steady state values in response to the disturbance. Fortunately, the effect of the disturbance is only temporary if the DCO is monotonic. For example, if the digital control word drifts higher (or lower) due to a disturbance, the DPLL will detect that the output frequency is too high (or too low) and will decrease (or increase) the average value of the digital control word to correct the error. If the DCO is not strictly monotonic, the DPLL may adjust the digital word in an erroneous direction and cause increased jitters or loop instability. [0011]One way to guarantee strict monotonicity in a DCO is to use a thermometer-code decoding scheme. Table 1 illustrates one example of a thermometer-code decoding scheme for mapping a digital control word W into eight binary data (e.g., D0, D1, . . . D7). Referring to the aforementioned LC oscillator by way of example, every incremental change in the digital control word W results in an additional control bit turning on to increase the total effective capacitance. Thus, monotonicity is guaranteed. It is generally difficult to ensure monotonicity without using the thermometer-code decoding scheme. The thermometer-code decoding scheme, however, usually requires a very high number of switched capacitors. What is needed is a DCO with a reduced number of switched elements and that still virtually guarantees monotonicity. TABLE-US-00001 TABLE 1 W 0 1 2 3 4 5 6 7 8 D[0] 0 1 1 1 1 1 1 1 1 D[1] 0 0 1 1 1 1 1 1 1 D[2] 0 0 0 1 1 1 1 1 1 D[3] 0 0 0 0 1 1 1 1 1 D[4] 0 0 0 0 0 1 1 1 1 D[5] 0 0 0 0 0 0 1 1 1 D[6] 0 0 0 0 0 0 0 1 1 D[7] 0 0 0 0 0 0 0 0 1 SUMMARY OF THE INVENTION [0012]The present invention solves these and other problems by providing a DAC (or digitally controlled analog circuit) comprising a finite state machine configured for receiving a digital input word (or digital control word) and generating at least a first digital code and a second digital code based on the digital input word in a manner determined by a state of the finite-state machine. In one embodiment, the finite state machine makes a state transition upon detecting a wrap-around condition in the second digital code. In one embodiment, the finite state machine changes states to improve monotonicity for the DAC during steady state operations without having to rely on a strictly thermometer-code decoding scheme. [0013]In one application, the digital input word is mapped such that the first digital code represents most significant bits (MSBs) of the digital input word and the second digital code represents least significant bits (LSBs) of the digital input word. One way to detect the wrap-around condition is to determine when the second digital code increases in value in response to a decrease in value of the digital input word or decreases in value in response to an increase in value of the digital input word. In one embodiment, the first digital code has a first range of values and the second digital code has a second range of values that partially overlaps with the first range of values. For example, the second digital code has a maximum value that is greater than (e.g., at least twice) a value represented by a LSB of the first digital code. [0014]In one embodiment, the finite state machine has a first state and a second state. The second digital code is generated in the first state by performing a modulo operation with the digital input word as a dividend. The second digital code is generated in the second state by performing a modulo operation with a sum of the input word and an offset as a dividend. A common divisor is used in the modulo operation of the first state and the modulo operation of the second state. In one embodiment, the offset has a value that is less than (e.g., approximately half of) a value of the common divisor. [0015]In one embodiment, the DAC further comprises a first decoder and a second decoder (e.g., binary code decoders or thermometer code decoders). The first decoder maps the first digital code into a first group of binary data and a first switched-circuit array can generate a first analog output in response to the first group of binary data. The second decoder maps the second digital code into a second group of binary data and a second switched-circuit array can generate a second analog output in response to the second group of binary data. A combination of the first analog output and the second analog output results in an analog output signal corresponding to the digital input word. For example, each group of binary data controls a group of switched circuits in the respective switched-circuit array (e.g., a digitally controlled variable capacitor or a plurality of switched current sources) to generate an analog output that is provided to a common circuit node corresponding to an output of the DAC. In one application, the DAC is used in a digitally controlled oscillator and the analog output is a variable capacitance that determines an oscillation frequency in accordance with the digital input word. [0016]In one embodiment, a method for converting a digital input word into an analog output signal (or digitally controlling an analog circuit) comprises generating a first digital code and a second digital code based on the digital input word in a scheme determined by a value of a state variable. For example, the method toggles (or switches) between a first algorithm and a second algorithm to generate the second digital code, wherein the toggling occurs whenever the second digital code makes an abrupt (or sudden) change from a relatively low value (e.g., a value close to a minimum value) to a relatively high value (or a value close to a maximum value) or from a relatively high value to a relatively low value within a short period of time (e.g., 1-2 clock cycles or a low number of clock cycles). [0017]In one embodiment, the first digital code represents the MSBs of the digital input word and the second digital code represents LSBs of the digital input word. One method for detecting abrupt changes (e.g., a boundary condition or a wrap-around condition) in the second digital code comprises determining when the second digital code increases in value in response to a decrease in value of the digital input word or decreases in value in response to an increase in value of the digital input word. The first digital code and the second digital code can have overlapping ranges of value. In one embodiment, the LSB of the first digital code has a value that is approximately half of a maximum value of the second digital code. [0018]In one embodiment, the first algorithm comprises a first modulo operation with the digital input word as a dividend and the second algorithm comprises a second modulo operation with a sum of the digital input word and an offset as a dividend. A common divisor is used in the first modulo operation and the second modulo operation with the common divisor having a value that is greater than (e.g., approximately twice of) a value of the offset. The first digital code is generated by dividing a difference between the digital input word and the second digital code by the offset. [0019]The first digital code is converted into a first analog output and the second digital code is converted into a second analog output, wherein the combination of the first analog output and the second analog output results in an analog signal corresponding to the digital input word. In one embodiment, the first digital code and the second digital code are decoded into respective first and second groups of binary data. In one application, the first digital code is mapped into the first group of binary data using a binary code decoder while the second digital code is mapped into the second group of binary data using a thermometer code decoder. The first group of binary data controls a first group of switches in a first switched-circuit array and the second group of binary data controls a second group of switches in a second switched-circuit array. The analog signal is generated by coupling an output of the first switched-circuit array with an output of the second switched-circuit array. Continue reading... Full patent description for Digital-to-analog converter and method thereof Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Digital-to-analog converter and method thereof patent application. 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