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Digital communication system and methodRelated Patent Categories: Pulse Or Digital Communications, Equalizers, Automatic, Adaptive, Decision Feedback EqualizerDigital communication system and method description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070242742, Digital communication system and method. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application claims the benefit of and priority to U.S. Provisional Application Ser. No. 60/364,430, entitled "Equalization In Digital Video Interfaces," and filed on Mar. 15, 2002, and U.S. Provisional Application Ser. No. 60/441,010, entitled "Systems And Methods For Data Communication And Transmission," and filed on Jan. 17, 2003. The entire disclosures of Application Ser. Nos. 60/364,430 and 60/441,010 are incorporated herein by reference. This application is also a divisional of U.S. Ser. No. 10/388,916, filed on Mar. 14, 2003. The entire disclosure of this prior, parent application is also incorporated herein by reference. BACKGROUND [0002] 1. Technical Field [0003] This application generally relates to digital communication systems and methods, and particularly relates to Digital Visual Interface (DVI) communications. [0004] 2. Description of the Related Art [0005] The Digital Visual Interface (DVI) Specification, Revision 1.0, dated Apr. 2, 1999, and published by Digital Display Working Group, provides for a high speed digital connection for visual data types that is display technology independent. A DVI interface is typically focused on providing a connection between a computer and the computer display device. A DVI system uses a transition minimized differential signal (TMDS) for a base electrical connection, in which 8 bits of data are encoded into a 10-bit, transition minimized DC balanced character. [0006] DVI accommodates several different serial signal rates, the highest of which is a signal rate of 1650 Mb/s. This signal rate corresponds to a data rate of 825 MHz. The DVI data may be transmitted over a video bus in a computer device, such as in laptop computer, or may be transmitted over a cable that is external to a computer device, such as a video cable used to connect a remote monitor to a computer. Typically, cables over short distances and low frequencies can be considered ideal channels having minimal loss and a bandwidth much greater than the input signal. The ideal cable with infinite bandwidth produces no dispersion of the input data. [0007] Real cables, however, have a loss characteristic that is a function of the data frequency and the cable length. Thus, the longer the cable length, the greater the loss characteristic. In practical applications, the attenuation of the high frequency components of the DVI data signal at 1650 MHz typically limits DVI cable lengths to about 5 meters. [0008] Equalizers may be used to restore the integrity of the DVI data so that the cable length between the source and the destination does not reduce the system performance. Many equalizers comprise a differential pair having an automatic gain control (AGC) feedback block between the output of the differential pair and the inputs of the differential pair. Additionally, many of these differential pairs utilize inductors, which demand a relatively large amount of semiconductor area and are susceptible to noise. [0009] The DVI specification also supports the VESA Display Data Channel (DDC), which enables the computer display, the computer, and a graphics adapter to communicate and automatically configure the system to support different features available in the computer display. The DDC link is typically a lower bandwidth signal, e.g., 400 kHz, and thus may be transmitted over a longer cable length than the DVI data signal. However, the DDC cable is typically not terminated in an impedance match, and thus reflections in the DDC cable may degrade the DDC signal as the DDC cable length increases. Additionally, the bandwidth of the DDC signal is limited by the amount of pull-up current injected into the DDC cable during a transition of the data signal from a low voltage level to a high voltage level. SUMMARY [0010] A digital communication system for transmitting and receiving Digital Visual Interface (DVI) communication data signals and Display Data Channel (DDC) communication signals over a transmission line comprises an open-loop equalizer circuit and a DDC extension circuit. The open-loop equalizer circuit is operable to receive DVI communication signals transmitted over the transmission line and output equalized DVI communication data signals. The DDC extension circuit is operable to inject a boost current at the receive end of the transmission line during a positive transition in the DDC communication signal, and clamp the receive end of the transmission line during a negative transition of the DDC communication signal. BRIEF DESCRIPTION OF THE DRAWINGS [0011] FIG. 1 is a block diagram of a DVI communication system; [0012] FIG. 2 is a block diagram of a digital communication system comprising equalizers and a DDC extender circuit; [0013] FIG. 3 is a block diagram of an equalizer configured to equalize data signals received at a receive end of a transmission line; [0014] FIG. 4 is a block diagram of an equalizer configured to pre-emphasize data signals to be transmitted on the transmission line. [0015] FIG. 5 is a block diagram of a pair of equalizers, the first equalizer configured to pre-emphasize data signals to be transmitted on the transmission line, and the second equalizer configured to equalize data signals received at a receive end of the transmission line; [0016] FIG. 6A is a block diagram of a receive side of the system of FIG. 3; [0017] FIG. 6B is a block diagram of a transmit side of the system of FIG. 4; [0018] FIG. 7 is a block diagram of an open-loop equalizer stage utilized in the systems of FIGS. 3-6B; [0019] FIG. 8 is a timing diagram of one DC pulse in a DC balanced data signal and a corresponding differential signal transmitted over the transmission line and equalized by the open-loop equalizer stage of FIG. 7; [0020] FIG. 9 is a block diagram of an input follower stage implemented at the input open-loop equalizer stage of FIG. 7; Continue reading about Digital communication system and method... Full patent description for Digital communication system and method Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Digital communication system and method patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Digital communication system and method or other areas of interest. ### Previous Patent Application: Multi-pair gigabit ethernet transceiver having a single-state decision feedback equalizer Next Patent Application: One-sample-per-bit decision feedback equalizer (dfe) clock and data recovery Industry Class: Pulse or digital communications ### FreshPatents.com Support Thank you for viewing the Digital communication system and method patent info. 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