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  Digital background calibration for time-interlaced analog-to-digital convertersThe Patent Description & Claims data below is from USPTO Patent Application 20070146181. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD OF THE INVENTION [0001] The present invention is directed, in general, to analog-to-digital conversion and, more specifically, to an apparatus and method for calibrating time-interlaced analog-to-digital converters. BACKGROUND OF THE INVENTION [0002] The increasing interest in higher data rate communication applications requires high-speed and high-resolution analog-to-digital converters (ADCs). One way of achieving such ADCs is to employ a time-interleaved architecture. Time-interleaved architectures provide a benefit of increased sampling rate for an analog signal and may employ a broad spectrum of ADC technologies. However, this benefit is usually achieved at the expense of both larger semiconductor die area and power consumption. [0003] Time-interleaved ADCs (TIADCs) also generally provide conversion-related errors due to mismatches among channel ADCs that occur in the areas of offset, gain and timing. These mismatches cause spurious components in the spectrum of the TIADC thereby generally degrading the signal-to-noise-and-distortion ratio (SNDR) of the TIADC. In particular, timing mismatch errors are a primary limiting factor and give rise to higher noise power in the overall output. Such timing mismatches have generally two different aspects. These include random sampling jitter and fixed periodic timing-skew among different channels. The use of sample-and-hold amplifiers reduces timing mismatch, but usually limits the overall throughput speed of the TIADC. [0004] Accordingly, what is needed in the art is an enhanced way to correct timing errors inherent in the use of multiple ADCs in a time-interleaved architecture. SUMMARY OF THE INVENTION [0005] To address the above-discussed deficiencies of the prior art, various embodiments provide background calibrators. In one embodiment, the background calibrator includes a TIADC having a parallel array of time-interleaved main signal processors, each main signal processor including an ADC connected to a corresponding output FIR filter. The background calibrator also includes an auxiliary signal processor having an ADC connected to at least one corresponding output FIR filter. Additionally, the background calibrator further includes a timing calibration circuit, wherein the timing calibration circuit is configured to select one of the main signal processors, exchange the auxiliary signal processor with the selected main signal processor in the TIADC, and connect the selected main signal processor to the timing calibration circuit. [0006] In an alternative embodiment, the timing calibration circuit is further configured to reduce a timing mismatch of the selected main signal processor based on interpolation quantities and timing mismatch operations defined for calibration of the auxiliary signal processor. [0007] In another aspect, the present invention provides a method for calibrating a TIADC. The method includes selecting a main signal processor, which includes an ADC connected to a corresponding output FIR filter, from a parallel array of time-interleaved main signal processors in the TIADC. The method also includes exchanging an auxiliary signal processor, which includes an ADC connected to at least one corresponding output FIR filter, with the selected main signal processor and connecting the selected main signal processor for calibration. In an alternative embodiment, the method further includes reducing a timing mismatch of the selected main signal processor based on interpolation quantities and timing mismatch operations defined for calibration of the auxiliary signal processor. [0008] The foregoing has outlined preferred and alternative features of various embodiments, so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the embodiments will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS [0009] For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [0010] FIG. 1A illustrates a block diagram of an embodiment of a background calibrator constructed in accordance with the principles of the present invention; [0011] FIG. 1B illustrates an alternative connection of the background calibrator of FIG. 1A constructed in accordance with the principles of the present invention; [0012] FIG. 2 illustrates an embodiment of an interpolation chart constructed in accordance with the principles of the present invention; [0013] FIG. 3 illustrates a power spectral density diagram associated with a TIADC as was discussed with respect to FIGS. 1A and 1B; [0014] FIG. 4 illustrates an SNDR chart showing uncalibrated and calibrated responses for a TIADC system constructed in accordance with the principles of the present invention; and [0015] FIG. 5 illustrates a flow diagram of an embodiment of a method for calibrating a TIADC carried out in accordance with the principles of the present invention. DETAILED DESCRIPTION [0016] Referring initially to FIG. 1A, illustrated is a block diagram of an embodiment of a background calibrator, generally designated 100, constructed in accordance with the principles of the present invention. The background calibrator 100 includes a time-interleaved analog-to-digital converter (TIADC) 105 coupled to input and output switch banks 110, 115, an auxiliary signal processor 120 also coupled to the input and output switch banks 110, 115 and a timing calibration circuit 125 coupled to the input and output switch banks 110, 115 and a filter coefficient switch 135. [0017] In the illustrated embodiment, the TIADC 105 includes a parallel array of four main signal processors 105.sub.1-105.sub.4, although generally, any plurality of such processors may be employed as appropriate to a particular application. Each of the main signal processors 105.sub.1-105.sub.4 includes a main analog-to-digital converter (ADC) and a corresponding output FIR filter (i.e., ADC.sub.1-ADC.sub.4 and corresponding FIR.sub.1-FIR.sub.4). The auxiliary signal processor 120 includes a calibration ADC and four calibration output FIR filters (i.e., ADC.sub.CAL and corresponding FIR.sub.CAL1-4). [0018] Each first input pole of the input switch bank 110 is connected to an analog input signal bus 106, and each second input pole of the input switch bank 110 is connected to a ramp input signal bus 107. Similarly, each first output pole of the output switch bank 115 is connected to a digital output signal bus 116. Each second output pole of the output switch bank 115, associated with the main signal processors 105.sub.1-105.sub.4, is connected to a mismatch calculation input 117 of the timing calibration circuit 125. Similarly, a second output pole of the output switch bank 115, associated with the auxiliary signal processor 120, is connected to an interpolation input 118 of the timing calibration circuit 125. [0019] The timing calibration circuit 125 includes a first register 126 containing initial digitized data stored in a first register (1), a digital interpolation module 127, a register array 128 containing interpolated data stored in a second register (2), a third register (3) and a fourth register (4) and a mismatch calculation module 129 that provides a mismatch calculation output 130 connected to the filter coefficient switch 135. Continue reading... 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