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Diffusion barrier for damascene structuresRelated Patent Categories: Semiconductor Device Manufacturing: Process, Coating With Electrically Or Thermally Conductive Material, To Form Ohmic Contact To Semiconductive Material, Contacting Multiple Semiconductive Regions (i.e., Interconnects), Multiple Metal Levels, Separated By Insulating Layer (i.e., Multiple Level Metallization), With Formation Of Opening (i.e., Viahole) In Insulative LayerDiffusion barrier for damascene structures description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060099802, Diffusion barrier for damascene structures. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD [0001] The present invention relates generally to semiconductors and, more particularly, to a semiconductor structure with a barrier layer in a damascene opening and a method for forming such a semiconductor structure in an integrated circuit. BACKGROUND [0002] Complementary metal-oxide-semiconductor (CMOS) technology is the dominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits today. Size reduction of the semiconductor structures has provided significant improvement in the speed, performance, circuit density, and cost per unit function of semiconductor chips over the past few decades. Significant challenges, however, are faced as the sizes of CMOS devices continue to decrease. [0003] One such challenge is the fabrication of interconnect structures. CMOS devices typically include semiconductor structures, such as transistors, capacitors, resistors, and the like, formed on a substrate. One or more conductive layers formed of a metal or metal alloy separated by layers of a dielectric material are formed over the semiconductor structures to interconnect the semiconductor structures and to provide external contacts to the semiconductor structures. Openings (e.g., contacts and vias in conventional metal interconnect structures, trenches and vias in damascene structures, or the like) are formed in the dielectric layers to provide an electrical connection between metal layers and/or a metal layer and a semiconductor structure. [0004] Generally, one or more adhesion/barrier layers are formed in the openings to prevent electron diffusion from the conductive material, e.g., copper, aluminum, or the like, into the surrounding dielectric material and to enhance the adhesive properties of the conductive material to the dielectric material. For example, it is common to utilize a first barrier layer formed of tungsten, titanium or tantalum, which provides good adhesive qualities to the dielectric layer. A second barrier layer is commonly formed of tungsten nitride, titanium nitride or tantalum nitride, which provides good adhesion qualities to the first barrier layer and a filler material, such as tungsten, aluminum or copper that may be used to fill the openings, such as contact, trench or via. [0005] However, the dielectric materials in which the openings are formed typically comprise a porous material, particularly with low-K dielectric materials having a dielectric constant less than about 2.75. The sidewall of the openings may be damaged during an etching and/or ashing process while forming the openings. The damaged sidewalls of the openings in the porous low-K dielectric layer may become more porous and rougher. As a result, a barrier layer formed over the sidewalls of the openings may be non-uniform, thereby allowing conductive material to diffuse into the porous low-K materials. In these situations, the non-uniform barrier layer may not provide an adequate diffusion barrier. This diffusion may result in failures and other reliability problems, particularly as design sizes decrease. Therefore, there is a need for a barrier layer that prevents or reduces diffusion. SUMMARY OF THE INVENTION [0006] These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention which provides a semiconductor structure with a barrier layer in a damascene opening. [0007] In accordance with an embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure comprises an opening defined through a porous low-K dielectric layer formed on a substrate. A protecting layer is formed on the dielectric layer along the sidewalls of the opening to protect the porous low-K dielectric layer along the sidewalls of the opening. The protecting layer preferably comprises more carbon concentration than the porous low-K dielectric layer and may comprise a nitrogen-containing, an oxygen-containing, a silicon-containing, a carbon-containing material, or the like. A barrier layer and a conductive material may be used to fill the opening. [0008] In accordance with another embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure comprises an opening defined through a porous low-K dielectric layer formed on a substrate. The sidewalls of the openings in the dielectric layer may comprise a carbonated, nitrogen or oxidized portion along the sidewall of the opening to protect the porous low-K dielectric layer on the sidewall of the opening. A barrier layer and a conductive material may be used to fill the opening. [0009] In accordance with yet another embodiment of the present invention, a semiconductor structure is provided. A porous low-K dielectric layer is formed on a substrate, and an opening is formed through the porous low-K dielectric layer. The pores of the dielectric layer along the sidewalls of the opening are at least partially sealed. One or more barrier layers are formed along the sidewalls of the opening, and a conductive material may be used to fill the opening. [0010] In accordance with yet another embodiment of the present invention, a method for fabricating a semiconductor structure with a pore-sealing process is provided. The method includes providing a substrate with a porous low-K dielectric layer formed thereon; forming an opening through the dielectric layer; forming a protecting layer on the sidewall of the opening; the protecting layer comprising a higher carbon concentration than the porous low-K dielectric layer; and forming a first barrier layer over the opening. The protecting layer may comprise an oxygen-containing or nitrogen-containing material. [0011] In accordance with yet another embodiment of the present invention, a method for fabricating a semiconductor structure with a pore-sealing process is provided. The method includes providing a substrate with a porous low-K dielectric layer formed thereon; forming an opening through the dielectric layer; performing a plasma treatment on the sidewall of the opening, the plasma treatment resulting in a carbonated, nitrogenated and/or oxidized portion of the porous low-K dielectric layer along the sidewall of the opening. A barrier layer may be subsequently formed along the sidewalls of the opening and the opening filled with a conductive material. [0012] It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS [0013] For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [0014] FIGS. 1a-1e illustrate steps that may be performed to fabricate barrier layers in accordance with a first embodiment of the present invention; [0015] FIGS. 2a-2d illustrate steps that may be performed to fabricate barrier layers in accordance with a second embodiment of the present invention; and [0016] FIG. 3 illustrates an element analysis of a cross-section of a via formed in accordance with an embodiment of the present invention. DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS [0017] The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed herein are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention. [0018] Referring now to FIG. 1a, a substrate 100 is provided having a conductive layer 110, an etch stop layer 112, and an IMD layer 114. Although it is not shown, the substrate 100 may include circuitry and other structures. For example, the substrate 100 may have formed thereon transistors, capacitors, resistors, interconnects and the like. In an embodiment, the conductive layer 110 is a metal layer that is in contact with electrical devices or another metal layer. [0019] The conductive layer 110 may be formed of any conductive material, but an embodiment of the present invention has been found to be particularly useful in applications in which the conductive layer 110 is formed of copper. As discussed above, copper provides good conductivity with low resistance. The etch stop layer 112 provides an etch stop that may be used to selectively etch the IMD layer 114 in a later processing step. In an embodiment, the etch stop layer 112 may be formed of a dielectric material such as a silicon-containing material, a nitrogen-containing material, an oxygen-containing material, a carbon-containing material or the like. The IMD layer 114 is preferably formed of a low-K dielectric material, such as a carbon-containing material, a nitrogen-containing material, an oxygen-containing material, or the like. The carbon-containing material, nitrogen-containing material, or oxygen-containing material of the IMD layer 114 may be a carbon-doped material, a nitrogen-doped material, or an oxygen-doped material. An embodiment of the present invention may be useful when using dielectric materials having a dielectric constant less that about 3.0. Other embodiments of the present invention may be particularly useful when dielectric materials having a dielectric constant less that about 2.75 are used. Continue reading about Diffusion barrier for damascene structures... Full patent description for Diffusion barrier for damascene structures Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Diffusion barrier for damascene structures patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. 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