| Differential difference amplifier -> Monitor Keywords |
|
|
  Differential difference amplifierThe Patent Description & Claims data below is from USPTO Patent Application 20070222514. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD [0001] This invention generally relates to differential difference amplifiers. BACKGROUND [0002] Low Voltage Differential Signaling (LVDS) interfaces are increasingly used for the large scale integration of electronic consumer products. An LVDS receiver comprising at least one differential difference amplifier (DDA) is used to receive and amplify an LVDS signal for use by other electronic circuits. [0003] An exemplary version of a conventional LVDS receiver 110 is illustrated in the schematic diagram of FIG. 1. This LVDS receiver 110 comprises two DDA's 120a,b, one differential amplifier 130, and a multiplexer 140. A conventional embodiment of the individual DDA's 120a and 120b is illustrated in the schematic diagram of FIG. 2. This DDA 120 comprises a first pair of p-channel metal-oxide-semiconductor (PMOS) transistors 210a,b and a second pair of PMOS transistors 220a,b. The DDA 120 further comprises four n-channel metal-oxide-semiconductor (NMOS) transistors 230a-230d and four PMOS transistors 240a-240d, configured as shown in FIG. 2. [0004] However, the conventional LVDS receiver 110 of FIG. 1 is susceptible to signal noise. Also, this LVDS receiver 110 is not capable of operating at low voltages, as sometimes required by mobile applications. Furthermore, this conventional LVDS receiver 110 can malfunction when a common mode voltage of an input voltage pair (PAD, PADN) is close to V.sub.SS, e.g., ground, while the common mode voltage of a reference voltage pair (V.sub.ref1, V.sub.ref2) is close to V.sub.DD/2, where V.sub.DD corresponds to a power supply voltage. In this situation, the drain voltages of the first transistor pair 210a,b, shown in FIG. 2, are pulled to approximately the level of the drain voltages of the second transistor pair 220a,b. The respective drain-to-source voltages of the first transistor pair 210a,b and the second transistor pair 220a,b cause the first transistor pair 210a,b to operate in a "triode" region, which is also referred to as a "resistive" region, while the second transistor pair 220a,b operates in a "pentode" region, which is also referred to as a "saturation" region. This difference in the respective operating regions of the two transistor pairs 210a,b, 220a,b results in an output voltage V.sub.out at a node 250 having an amplitude that is not proportional to the difference between the differential of the input voltage pair (PAD, PADN) and the differential of the reference voltage pair (V.sub.ref1, V.sub.ref2). [0005] Another version of an LVDS receiver is the conventional differential operational amplifier (op-amp) 310 illustrated in the schematic diagram of FIG. 3. This differential op-amp 310 comprises NMOS FETs 320a-320j, PMOS FETs 330a-330j, resistors 340a-340c, a capacitor 350, and an inverter 360, configured as shown in FIG. 3. The differential op-amp 310 may permit operation across a wider common mode range (CMR). However, this differential op-amp 310 is also susceptible to signal noise and generally incapable of operating at low voltages. [0006] Thus, it is desirable to have a DDA adapted to operate effectively across a wider CMR. It is also desirable for the DDA to have increased tolerance to noise. It is still further desirable for the DDA to be able to operate at low voltages. SUMMARY [0007] A differential difference amplifier includes first and second low supply output terminals and first and second high supply output terminals, one or more of the first and second low supply output terminals and one or more of the first and second high supply output terminals being coupled to a low voltage terminal and a high voltage terminal, respectively. A first bias regulator comprises a first output terminal to supply a first bias voltage and a second output terminal to supply a second bias voltage. A second bias regulator comprises first and second output terminals. [0008] First, second, third, and fourth current control PMOS transistors are also provided, each having a gate, a source, and a drain. The sources of these transistors are coupled to one another and to the second high supply output terminal. The gates of the first and second current control PMOS transistors are coupled to first and second terminals of a first pair of differential input terminals, respectively. The gates of the third and fourth current control PMOS transistors are coupled to first and second terminals of a second pair of differential input terminals, respectively. [0009] The differential difference amplifier further comprises first and second load current control PMOS transistors, each having a gate, a source, and a drain. The sources of the first and second load current control PMOS transistors are coupled to the first high output terminal, and the gates of the first and second load current control PMOS transistors are coupled to the first output terminal of the first bias regulator. [0010] First, second, third, and fourth current control NMOS transistors are also provided, each having a gate, a source, and a drain. The sources of the first, second, third, and fourth current control NMOS transistors are coupled to each other and to the second low supply output terminal. The gates of the first and second current control NMOS transistors are coupled to the first and second terminals of the first pair of differential input terminals, respectively. The gates of the third and fourth current control NMOS transistors are coupled to the first and second terminals of the second pair of differential input terminals, respectively. [0011] The differential difference amplifier additionally includes first and second load current control NMOS transistors, each having a gate, a source, and a drain. The sources of the first and second load current control NMOS transistors are coupled to the first low supply output terminal, and the gates of the first and second load current control NMOS transistors are coupled to the second output terminal of the first bias regulator. [0012] First and second voltage control PMOS transistor circuits are further provided, each having a gate terminal, at least one source terminal, and a drain terminal. The at least one source terminal of the first voltage control PMOS transistor is coupled to the drains of the first and fourth current control PMOS transistors and to the drain of the first load current control PMOS transistor. The at least one source terminal of the second voltage control PMOS transistor circuit is coupled to the drains of the second and third current control PMOS transistors and to the drain of the second load current control PMOS transistor. The gate terminal of the first voltage control PMOS transistor circuit is coupled to the first output terminal of the second bias regulator. The gate terminal of the second voltage control PMOS transistor circuit is coupled to the second output terminal of the second bias regulator. [0013] In addition, first and second voltage control NMOS transistor circuits are provided, each having a gate terminal, at least one source terminal, and a drain terminal. The at least one source terminal of the first voltage control NMOS transistor circuit is coupled to the drains of the first and fourth current control NMOS transistors and to the drain of the first load current control NMOS transistor. The at least one source terminal of the second voltage control NMOS transistor circuit is coupled to the drains of the second and third current control NMOS transistors and to the drain of the second load current control NMOS transistor. The gate terminal of the first voltage control NMOS transistor circuit is coupled to the first output terminal of the second bias regulator. The gate terminal of the second voltage control NMOS transistor circuit is coupled to the second output terminal of the second bias regulator. [0014] The drain terminals of the second voltage control PMOS transistor circuit and the second voltage control NMOS transistor circuit are coupled to a first terminal of a pair of differential output terminals. The drain terminals of the first voltage control PMOS transistor circuit and the first voltage control NMOS transistor circuit are coupled to a second terminal of the pair of differential output terminals. [0015] In another embodiment, the gates of the first and second load current control PMOS transistors are coupled to the first and second output terminals, respectively, of the second bias regulator. The gates of the first and second load current control NMOS transistors are coupled to the first and second output terminals, respectively, of the second bias regulator. The gate terminal of the first voltage control PMOS transistor circuit is coupled to the first output terminal of the second bias regulator. The gate terminal of the second voltage control PMOS transistor circuit is coupled to the second output terminal of the second bias regulator. The gate terminal of the first voltage control NMOS transistor circuit is coupled to the first output terminal of the second bias regulator. The gate terminal of the second voltage control NMOS transistor circuit is coupled to the second output terminal of the second bias regulator. [0016] In yet another embodiment, the gates of the first and second load current control PMOS transistors are coupled to the first and second output terminals, respectively, of the second bias regulator. The gates of the first and second load current control NMOS transistors are coupled to the first and second output terminals, respectively, of the second bias regulator. The gate terminals of the first and second voltage control PMOS transistor circuits are coupled to the first output terminal of the first bias regulator. The gate terminals of the first and second voltage control NMOS transistor circuits are coupled to the second output terminal of the first bias regulator. BRIEF DESCRIPTION OF THE DRAWINGS [0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain advantages and principles of the invention. [0018] In the drawings, [0019] FIG. 1 is a schematic diagram of an embodiment of a conventional low voltage differential signaling (LVDS) receiver; [0020] FIG. 2 is a schematic diagram of an embodiment of a conventional differential difference amplifier (DDA) in the LVDS receiver of FIG. 1; Continue reading... Full patent description for Differential difference amplifier Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Differential difference amplifier patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Differential difference amplifier or other areas of interest. ### Previous Patent Application: Apparatus and method for processing of amplifier linearization signals Next Patent Application: Variable gain amplifier and communication apparatus Industry Class: Amplifiers ### FreshPatents.com Support Thank you for viewing the Differential difference amplifier patent info. IP-related news and info Results in 0.4404 seconds Other interesting Feshpatents.com categories: Daimler Chrysler , DirecTV , Exxonmobil Chemical Company , Goodyear , Intel , Kyocera Wireless , |
||
