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  Differential amplifying method and apparatus operable with a wide range input voltageThe Patent Description & Claims data below is from USPTO Patent Application 20060226908. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND [0001] 1. Field [0002] This patent specification relates to a method and apparatus for differential amplification used in an integrated circuit, and more particularly to a method and apparatus for differential amplification operable at a voltage of a relatively wide range. [0003] 2. Discussion of the Background [0004] Background differential amplifier circuits generally used are illustrated in FIGS. 1 and 2. A differential amplifier circuit 100 of FIG. 1 includes a differential transistor pair D101 formed by two N-channel transistors M1 and M2. Meanwhile, a differential amplifier circuit 200 of FIG. 2 includes a differential transistor pair D201 formed by two P-channel transistors M3 and M4. In each of the differential amplifier circuits 100 and 200, a constant current source CCS101 outputs a constant current ia. Further, a high-potential power supply voltage V1 is input in an input terminal IN1, and a low-potential power supply voltage V2 is input in an input terminal IN2. An output voltage Vout is output from an output terminal Vout. [0005] An input voltage for operating the differential amplifier circuits is limited in range due to threshold characteristics of the transistors. For example, the differential amplifier circuit 100 of FIG. 1 operates at an input voltage in a range from approximately 1 volt to a high-potential power supply voltage V1. On the other hand, the differential amplifier circuit 200 of FIG. 2 operates at an input voltage in a range from a low-potential power supply voltage V2 (e.g., an earth termination voltage) to a voltage approximately 1 volt lower than the high-potential power supply voltage V1. Meanwhile, as illustrated in FIG. 3, Japanese Examined Patent Publication No. 06-018309, for example, discloses another differential amplifier circuit which stably operates at an input voltage in a relatively wide range. [0006] The differential amplifier circuit 300 of FIG. 3 includes a constant current source CCS301 for outputting the constant current ia and a constant current source CCS302 for outputting a constant current ib. The differential amplifier circuit 300 of FIG. 3 further includes a differential transistor pair D302 formed by P-channel MOS (metal-oxide semiconductor) transistors (hereinafter referred to as PMOS transistors) M311 and M312. The differential transistor pair D302 corresponds to the differential amplifier circuit 200 of FIG. 2. Furthermore, the differential amplifier circuit 300 includes another differential transistor pair D301 formed by N-channel MOS transistors (hereinafter referred to as NMOS transistors) M302 and M303, an NMOS transistor M301 serving as a constant current source, and a current mirror circuit CM301 formed by PMOS transistors M304 and M305, which outputs a current approximately equal or proportional in amount to a current flowing through the NMOS transistor M302 to a drain of the PMOS transistor M312. The NMOS transistor M302 of the differential transistor pair D301 and the PMOS transistor M311 of the differential transistor pair D302 are respectively connected to an input terminal IN3. Meanwhile, the. NMOS transistor M303 of the differential transistor pair D301 and the PMOS transistor M312 of the differential transistor pair D302 are respectively connected to an input terminal IN4. [0007] The differential amplifier circuit 300 further includes a current mirror circuit CM302 formed by PMOS transistors M306 and M307, which outputs a current equal or proportional in amount to a current flowing through the NMOS transistor M303 to a drain of the PMOS transistor M311. Furthermore, the differential amplifier circuit 300 includes an NMOS transistor M321, which has a source connected to a connection point between a source of the NMOS transistor M302 and a source of the NMOS transistor M303, and a gate for receiving input of a predetermined reference voltage Vr. [0008] In addition, the differential amplifier circuit 300 includes a current mirror circuit CM303 formed by PMOS transistors M322 and M310, which serves as a constant current source for the differential transistor pair D302 (i.e., the differential amplifier circuit corresponding to the differential amplifier circuit 200 of FIG. 2). Specifically, the current mirror circuit CM303 outputs a current approximately equal or proportional in amount to the current flowing through the NMOS transistor M321 to respective sources of the PMOS transistors M111 and M112 which form the differential transistor pair D302. [0009] In the differential amplifier circuit 300, when an input common mode voltage (i.e., an average between a voltage input in the input terminal IN3 and a voltage input in the input terminal IN4) is close to the earth termination voltage, the NMOS transistors M302 and M303 are both turned off, and a current flowing through the NMOS transistor M301 flows into the NMOS transistor M321. Then, the current passes through the current mirror circuit CM303 including the PMOS transistors M322 and M310 and flows into each of the PMOS transistors M311 and M312 of the differential transistor pair D302. The PMOS transistor M310 of the current mirror circuit CM303 serves as a constant current source for the PMOS transistors M311 and M312. A half of a current output from the PMOS transistor M310 flows into the PMOS transistor M311, and the other half of the current flows into the PMOS transistor M312. The PMOS transistors M311 and M312 together serve as an amplifier circuit connected to a load formed by NMOS transistors M313 and M314. [0010] In the differential amplifier circuit 300, when the input common mode voltage increases, a current starts to flow into each of the NMOS transistors M302 and M303. Then, the current flowing into the NMOS transistor M321 decreases by an amount equal to an amount of a current flowed into the NMOS transistors M302 and M303. As a result, the current output from the PMOS transistor M310 also decreases. A current approximately equal or proportional in amount to the current flowing through the NMOS transistor M302 is output from the PMOS transistors M305 of the current mirror circuit CM301 and then is combined with a current output from the PMOS transistor M312. Accordingly, an amount of the thus combined currents is equal to a half amount of the current output from the NMOS transistor M301. Similarly, a current approximately equal or proportional in amount to the current flowing through the NMOS transistor M303 is output from the PMOS transistors M307 of the current mirror circuit CM302 and then is combined with a current output from the PMOS transistor M311. Accordingly, an amount of the thus combined currents is equal to the half amount of the current output from the NMOS transistor M301. [0011] If the input common mode voltage further increases and exceeds the reference voltage Vr input in the gate of the NMOS transistor M321, the NMOS transistor M321 is turned off, and all of currents supplied by the NMOS transistor M301 flow into the NMOS transistors M302 and M303. As described above, the current approximately equal or proportional in amount to the current flowing through the NMOS transistor M302 is output from the current mirror circuit CM301 and combined with the current output from the PMOS transistor M312. Meanwhile, the current approximately equal or proportional in amount to the current flowing through the NMOS transistor M303 is output from the current mirror circuit CM302 and combined with the current output from the PMOS transistor M311. Accordingly, the PMOS transistors M311 and M312 together serve as the amplifier circuit connected to the load formed by the NMOS transistors M313 and M314. The operation described above is observed in the differential amplifier circuit 300, when the input common mode voltage is equal to or lower than the high-potential power supply voltage V1. Further, a sum of currents flowing through the NMOS transistors M313 and M314, which together form the load, is equal in amount to the current flowing through the NMOS transistor M301. As a result, fluctuation in current gain caused by a difference in input voltages is reduced. [0012] The differential amplifier circuit 300 of FIG. 3 includes both of the differential PMOS transistor pair and the differential NMOS transistor pair. A drain of either one of the differential PMOS transistor pair and the differential NMOS transistor pair is used for outputting the output voltage Vout. For example, in the differential amplifier circuit 300, a drain of the PMOS transistor M311 is used for outputting the output voltage Vout. However, the upper limit of a drain voltage of the PMOS transistor M311 is equal to a voltage higher than the input voltage input in the input terminal IN3 of the PMOS transistor M311 by a threshold voltage of the PMOS transistor M311. As a result, the differential amplifier circuit 300 needs to include an output circuit or an amplifier circuit so as to increase a range of the output voltage Vout. In the differential amplifier circuit 300 thus configured, the range of the output voltage output from the drain of the PMOS transistor M311 varies depending on the input voltage. Also, due to configurations of the output circuit and the amplifier circuit provided at a following stage, currents for driving the output terminal OUT are different between when the output voltage Vout rises and when the output voltage Vout falls. As a result, rise and fall of an output signal vary depending on the input voltage, causing delay time. This causes a difference between the rising time and the falling time of the output signal. SUMMARY [0013] This patent specification describes a differential amplifying apparatus. In one example, a differential amplifying apparatus includes first and second differential transistor pairs and first to sixth current mirror circuits. The first differential transistor pair includes two transistors of a first polarity configured to be operated by a first predetermined constant current. The second differential transistor pair includes two transistors of a second polarity configured to be operated by a second predetermined constant current. The first current mirror circuit is configured to receive a first power supply voltage and output a current approximately equal or proportional in amount to a current flowing through one transistor of the first differential transistor pair. The second current mirror circuit is configured to be connected to an output terminal, receive the first power supply voltage, and output a current approximately equal or proportional in amount to a current flowing through the other transistor of the first differential transistor pair. The third current mirror circuit is configured to be connected to the output terminal, receive a second power supply voltage, and output a current input from the first current mirror circuit. The fourth current mirror circuit is configured to receive the second power supply voltage and output a current approximately equal or proportional in amount to a current flowing through one transistor of the second differential transistor pair. The fifth current mirror circuit is configured to be connected to the output terminal, receive the second power supply voltage, and output a current approximately equal or proportional in amount to a current flowing through the other transistor of the second differential transistor pair. The sixth current mirror circuit is configured to be connected to the output terminal, receive the first power supply voltage, and output a current input from the fourth current mirror circuit. [0014] Further, this patent specification described another differential amplifying apparatus. In one example, this differential amplifying apparatus includes first to fourth input terminals, an output terminal, first and second differential transistor pairs, and first to sixth current mirror circuits. The first input terminal is configured to receive a first power supply voltage, and the second input terminal is configured to receive a second power supply voltage. The output terminal is configured to output a differential amplified voltage. The first differential transistor pair is configured to be operated by a first predetermined constant current, and includes a first transistor of a first polarity having a gate connected to the third input terminal, and a second transistor of the first polarity having a gate connected to the fourth input terminal. The second differential transistor pair is configured to be operated by a second predetermined constant current, and includes a third transistor of a second polarity having a gate connected to the third input terminal, and a fourth transistor of the second polarity having a gate connected to the fourth input terminal. The first current mirror circuit is configured to receive the first power supply voltage and output a current approximately equal or proportional in amount to a current flowing through the first transistor. The second current mirror circuit is configured to be connected to the output terminal, receive the first power supply voltage, and output a current approximately equal or proportional in amount to a current flowing through the second transistor. The third current mirror circuit is configured to be connected to the output terminal, receive the second power supply voltage, and output a current input from the first current mirror circuit. The fourth current mirror circuit is configured to receive the second power supply voltage and output a current approximately equal or proportional in amount to a current flowing through the third transistor. The fifth current mirror circuit is configured to be connected to the output terminal, receive the second power supply voltage, and output a current approximately equal or proportional in amount to a current flowing through the fourth transistor. The sixth current mirror circuit is configured to be connected to the output terminal, receive the first power supply voltage, and output a current input from the fourth current mirror circuit. [0015] The differential amplifying apparatus may further include a second constant current source including a reference voltage source, a transistor of the first polarity, and a current mirror circuit. The reference voltage source may be configured to generate and output a predetermined reference voltage. The transistor of the first polarity may include a gate configured to receive the predetermined reference voltage, and a source connected to respective sources of the first and second transistors. The current mirror circuit may be configured to receive the first power supply voltage, and include an input terminal connected to a drain of the transistor of the first polarity, and an output terminal connected to a connection point connecting respective sources of the third and fourth transistors. [0016] In the differential amplifying apparatus, the predetermined reference voltage output from the reference voltage source may be set to be within a range of voltages input in the third and fourth input terminals to pass currents through each of the first and second differential transistor pairs. Preferably, a total operating current is substantially constant and is approximately equal to the first predetermined constant current. [0017] A preferred embodiment of the differential amplifying apparatus operates in a range from approximately the first power supply voltage to approximately the second power supply voltage, and the range does not vary according to an input voltage of the differential amplifying apparatus. In addition, in the preferred embodiment, a rise time of an output voltage of the differential amplifying apparatus is approximately equal to a fall time of the output voltage. [0018] This patent specification further describes a differential amplifying method. In one example, a differential amplifying method includes: providing a first differential transistor pair including two transistors of a first polarity, and a second differential transistor pair including two transistors of a second polarity; providing first to sixth current mirror circuits; connecting the second, third, fifth, and sixth current mirror circuits to an output terminal; supplying a first predetermined constant current to the first differential transistor pair; supplying a second predetermined constant current to the second differential transistor pair; inputting a first power supply voltage in the first, second, and sixth current mirror circuits; inputting a second power supply voltage in the third, fourth, and fifth current mirror circuits; causing the first current mirror circuit to output a current approximately equal or proportional in amount to a current flowing through one transistor of the first differential transistor pair; causing the second current mirror circuit to output a current approximately equal or proportional in amount to a current flowing through the other transistor of the first differential transistor pair; causing the third current mirror circuit to output a current input from the first current mirror circuit; causing the fourth current mirror circuit to output a current approximately equal or proportional in amount to a current flowing through one transistor of the second differential transistor pair; causing the fifth current mirror circuit to output a current approximately equal or proportional in amount to a current flowing through the other transistor of the second differential transistor pair; and causing the sixth current mirror circuit to output a current input from the fourth current mirror circuit. [0019] Further, this patent specification describes another differential amplifying method. In one example, this differential amplifying method includes: providing a first input terminal configured to receive a first power supply voltage, a second input terminal configured to receive a second power supply voltage, a third input terminal, a fourth input terminal, and an output terminal configured to output a differential amplified voltage; providing a first differential transistor pair including a first transistor of a first polarity having a gate connected to the third input terminal, and a second transistor of the first polarity having a gate connected to the fourth input terminal; providing a second differential transistor pair including a third transistor of a second polarity having a gate connected to the third input terminal, and a fourth transistor of the second polarity having a gate connected to the fourth input terminal; providing first to sixth current mirror circuits; connecting the second, third, fifth, and sixth current mirror circuits to an output terminal; supplying a first predetermined constant current to the first differential transistor pair; supplying a second predetermined constant current to the second differential transistor pair; inputting the first power supply voltage in first, second, and sixth current mirror circuits; inputting the second power supply voltage in third, fourth, and fifth current mirror circuits; causing the first current mirror circuit to output a current approximately equal or proportional in amount to a current flowing through the first transistor; causing the second current mirror circuit to output a current approximately equal or proportional in amount to a current flowing through the second transistor; causing the third current mirror circuit to output a current input from the first current mirror circuit; causing the fourth current mirror circuit to output a current approximately equal or proportional in amount to a current flowing through the third transistor; causing the fifth current mirror circuit to output a current approximately equal or proportional in amount to a current flowing through the fourth transistor; and causing the sixth current mirror circuit to output a current input from the fourth current mirror circuit. [0020] The differential amplifying method may further include: providing a reference voltage source, a transistor of the first polarity, and a current mirror circuit; connecting a source of the transistor of the first polarity to respective sources of the first and second transistors; connecting an input terminal of the current mirror circuit to a drain of the transistor of the first polarity; connecting an output terminal of the current mirror circuit to a connection point connecting respective sources of the third and fourth transistors; inputting the first power supply voltage in the current mirror circuit; and causing the reference voltage source to generate and input a predetermined reference voltage in a gate of the transistor of the first polarity. [0021] The differential amplifying method may further include setting the predetermined reference voltage output from the reference voltage source to be within a range of voltages input in the third and fourth input terminals to pass currents through each of the first and second differential transistor pairs. BRIEF DESCRIPTION OF THE DRAWINGS Continue reading... Full patent description for Differential amplifying method and apparatus operable with a wide range input voltage Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Differential amplifying method and apparatus operable with a wide range input voltage patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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