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  Dielectric gap fill with oxide selectively deposited over silicon linerUSPTO Application #: 20070087522Title: Dielectric gap fill with oxide selectively deposited over silicon liner Abstract: A thin layer of silicon is deposited within a high aspect ratio feature to provide a template for selective deposition of oxide therein. In accordance with one embodiment, amorphous silicon is deposited within a shallow trench feature overlying an oxide liner grown therein. After exposure to sputtering to remove the amorphous silicon from outside of the trench, oxide is selectively deposited over the amorphous silicon to fill the trench from the bottom up without voids, thereby creating a shallow trench isolation (STI) structure. Deposition of the amorphous silicon or other silicon containing layers allows the selective oxide deposition step to be integrated with a thermally-grown oxide trench liner. (end of abstract)
Agent: Townsend And Townsend And Crew LLP / Amat - San Francisco, CA, US Inventors: Srinivas Nemani, Shankar Venkataraman USPTO Applicaton #: 20070087522 - Class: 438424000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Formation Of Electrically Isolated Lateral Semiconductive Structure, Grooved And Refilled With Deposited Dielectric Material The Patent Description & Claims data below is from USPTO Patent Application 20070087522. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATION [0001] This application is a continuation of U.S. patent application Ser. No. 10/858,135, entitled "DIELECTRIC GAP FILL WITH OXIDE SELECTIVELY DEPOSITED OVER SILICON LINER," filed Jun. 1, 2004, the entire disclosure of which is incorporated herein by reference for all purposes. BACKGROUND OF THE INVENTION [0002] The present invention relates generally to the fabrication of integrated circuits. More particularly, the present invention is directed toward a method of performing gap-fill in integrated circuit devices. Merely by way of example, the invention has been applied to a method for providing self-planarized deposition of high quality dielectric layers for shallow trench isolation. The method can be applied to other applications as well such as inter-metal dielectric and pre-metal dielectric deposition. [0003] Semiconductor device geometries continue to decrease in size, providing more devices per unit area on a fabricated wafer. These devices are typically initially isolated from each other as they are built into the wafer, and they are subsequently interconnected to create the specific circuit configurations desired. Currently, some devices are fabricated with feature dimensions as small as 0.18 .mu.m. For example, spacing between devices such as conductive lines or traces on a patterned wafer may be separated by 0.18 .mu.m, leaving recesses or gaps of a comparable size. A nonconductive layer of dielectric material, such as silicon dioxide (SiO.sub.2), is typically deposited over the features to fill the aforementioned gaps (gap-fill) and insulate the features from other features of the integrated circuit in adjacent layers or from adjacent features in the same layer. [0004] Dielectric layers are used in various applications including shallow trench isolation (STI) dielectric for isolating devices and interlayer dielectric (ILD) formed between metal wiring layers or prior to a metallization process. In some cases, STI is used for isolating devices having feature dimensions as small as under about 0.5 .mu.m. In some of these cases, the aspect ratio of the depth to width of the trench to be filled exceeds 6:1. Planarization of dielectric layers has become increasingly important as the packing densities of semiconductor devices continue to grow. [0005] The planarization issue is described using an example of a typical process for forming an STI dielectric, commonly referred to as STI integration, as illustrated in FIGS. 1a-1h. In FIG. 1a, a silicon substrate 110 has deposited thereon a pad oxide layer 112 and a nitride layer 114 such as silicon nitride. The nitride layer 114 is typically deposited by low pressure chemical vapor deposition (LPCVD), and serves as an etch stop for chemical mechanical polishing (CMP). [0006] Referring to FIG. 1b, a bottom anti-reflective coating (BARC) 116 is formed above the nitride layer 114 for absorbing light reflected from the substrate 110 during photolithography. Typically an organic spin-on glass (SOG), the BARC 116 is needed typically for light having wavelengths of below about 248 nm, including deep ultraviolet (DUV) and far ultraviolet (FUV) light. A photoresist 118 is formed over the BARC 116 and exposed using a mask (not shown) which defines the location of the trenches. [0007] The exposed photoresist is then stripped to leave open areas for forming the trenches. Typically, a plasma etch is performed to etch the open areas through the BARC 116, the nitride 114, pad oxide 112, and silicon substrate 110 to form the trenches 120, as shown in FIG. 1c. [0008] After the remaining photoresist 118 and BARC 116 are removed, a thermal oxide 122 is typically grown on the surfaces of the trenches 120 (trench bottom 124 and trench wall 126) to repair the plasma damage to the silicon substrate 110, as illustrated in FIG. 1d. [0009] A dielectric layer 128 is then deposited over the thermal oxide 122 to fill the trenches 120 and cover the nitride layer 114. This dielectric layer 128 is often referred to as a trench oxide filling layer. Typical dielectric layers are formed from oxide materials such as silicon dioxide or silicate glass. As shown in FIG. 1e, the surface profile of the deposited dielectric layer 128 is stepped and generally resembles the shape of the trenched substrate 110. The surface profile is more uniform in dense fields with closely space narrow trenches than in open fields with wide trenches. As seen in FIG. 1e, a step height 130 is formed in the dielectric profile between the dense field 134 and the open field 132. [0010] Because of the step height 130, it is not practicable to apply CMP directly after the dielectric layer deposition step to planarize the dielectric layer 128 because otherwise a dishing effect in the open field 132 will result with CMP, as seen in FIG. 1h. Instead, a reverse mask and etch procedure is used to etch the extra oxide to obtain a more planar surface profile as illustrated in FIG. 1f. This procedure typically involves the steps of photoresist deposition, reverse masking, cure, etched photoresist removal, etchback, and removal of remaining photoresist. [0011] A CMP procedure is then applied to the structure of FIG. 1f to globally planarize the surface of the filled substrate 110 as shown in FIG. 1g. The reverse mask and etch procedure necessitated by the step height effect adds significant cost and complexity to the planarization procedure, for example, due to the added lithography steps involved. [0012] From the discussion above, it is seen that multiple steps, including additional photolithography steps (which require expensive equipment), are needed to provide STI as described in relation to FIGS. 1a-1h. However, it is desirable to reduce the number of steps (and related equipment, especially photolithography equipment which requires expensive lenses, light sources, etc.) and to obtain improved results in order to provide a more economic and efficient manufacturing process. For example, one way to obtain improved results is to provide a self-planarized, high quality trench oxide filling layer at a reduced cost. [0013] A number of procedures are known for depositing dielectric layers such as the gap-fill dielectric 128 for the trench oxide filling layer in the example shown in FIG. 1e. One type of process employs O.sub.3 (ozone) and TEOS (tetraethylorthosilicate) for depositing a dielectric film such as silicate glass. Such deposited films are commonly referred to as "O.sub.3/TEOS films." Such O.sub.3/TEOS processes have a surface sensitivity which increases as the O.sub.3/TEOS ratio increases. Due to the surface sensitivity, the dielectric deposition rate varies in accordance with the properties of the material of the underlying layer. [0014] It is known to minimize the surface sensitivity by depositing a surface insensitive barrier layer prior to the O.sub.3/TEOS film deposition. For instance, one known process involves a plasma-enhanced TEOS (PETEOS) deposition, followed by a surface treatment and then a thin cap TEOS layer. This process undesirably requires additional process steps. [0015] Another known method is to lower the surface sensitivity by decreasing the O.sub.3/TEOS ratio. However, lowering the O.sub.3/TEOS ratio tends to undesirably result in a more porous dielectric film. This is particularly problematic when the dielectric film is used for isolation purposes. One way to address this concern has been to raise the process temperature to above about 500.degree. C., but raising the process temperature is often undesirable. Alternatively, an additional anneal process after the deposition of the trench oxide filling layer and sandwiching PETEOS layers has been used to densify the trench oxide filling layer. This method, however, suffers from the need to perform an extra step. [0016] Instead of minimizing the surface sensitivity, some have utilized the deposition rate dependence of O.sub.3/TEOS films to perform gap fill for a trenched silicon substrate wherein the side walls of the trench are covered with thermal oxide spacers. Using an atmospheric pressure chemical vapor deposition (APCVD) O.sub.3/TEOS deposition and an ozone concentration of 5%, it was reported that faster film growth on the bottom silicon than on the side wall spacers precluded void formation to achieve void-free gap fill. [0017] Others have investigated the feasibility of forming a planarized inter-metal dielectric (IMD) by taking advantage of the surface sensitivity of O.sub.3/TEOS and similar materials such as O.sub.3-octamethylcyclotetrasiloxane (OMTC). Researchers have reported difficulties in controlling the different deposition rates to achieve planarity. For instance, significant elevations have been observed at the edges of aluminum metal lines caused by the different deposition rates of the O.sub.3/TEOS on a TiN anti-reflective coating (ARC) layer on top of the aluminum and the aluminum side walls. Some of these same researchers have reported more satisfactory planarization results for depositing SiO.sub.2 layers on an aluminum interconnect built upon a phosphorus glass (PSG) level using O.sub.3-OMTC. [0018] In light of the above, attempts to obtain planarity by depositing surface sensitive dielectric layers have not always been successful. In addition, the inventors have discovered that these methods may produce dielectric layers that do not have the desired quality. What is needed are more efficient and economic methods for self-planarized deposition of a high quality trench oxide filling layer for STI integration. SUMMARY OF THE INVENTION [0019] According to embodiments of the present invention, a method for fabricating integrated circuits is provided. More particularly, the present invention is directed toward a method of performing gap-fill in integrated circuit devices. Merely by way of example, the invention has been applied to a method for providing self-planarized deposition of high quality dielectric layers for shallow trench isolation. The method can be applied to other applications as well, for example to deposition of pre-metal dielectric (PMD) between raised features present on the surface of a workpiece. [0020] An embodiment of a method in accordance with the present invention for depositing a fill layer in a recess, comprises, disposing in a substrate processing chamber a substrate having a recess, and forming a first insulating layer within the recess. A silicon containing layer is deposited on the substrate, and an upper portion of the silicon containing layer is removed while maintaining a portion of the silicon containing layer within the recess. A second insulating layer is selectively deposited within the recess and then etched, and a third insulating layer is deposited on the substrate and over the second insulating layer to form a capping layer. [0021] An embodiment of a method of performing gap-fill in a high aspect ratio recess, comprises, forming an oxide liner within a high aspect ratio recess on a semiconductor workpiece, and depositing a silicon containing liner on the workpiece and within the recess over the oxide liner. The silicon containing liner is etched to remove a portion of the silicon containing liner from outside of the recess and from an upper portion of the recess. A first insulating layer is selectively deposited within the trench overlying the silicon containing liner. The first insulating layer is etched, and then a second insulating layer is deposited. Continue reading... Full patent description for Dielectric gap fill with oxide selectively deposited over silicon liner Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Dielectric gap fill with oxide selectively deposited over silicon liner patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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