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  Device-managed host bufferUSPTO Application #: 20060112252Title: Device-managed host buffer Abstract: A method and apparatus is provided to virtually increase the size of the memory cache of a peripheral device without additional cost. A portion of the memory space of a host computer is used as additional cache memory for the peripheral device. The peripheral device and the host computer may be interfaced with an interface that has a first-party direct memory access (FPDMA) mechanism, for example, IEEE 1394 or Serial ATA. FPDMA allows the peripheral device to access the memory space of the host computer under the control of the peripheral device. The host computer provides the peripheral device with the location of the additional cache memory. The peripheral device can transfer data to and from the additional cache memory via FPDMA. The peripheral device effectively manages the additional cache memory as part of the peripheral device's own cache. (end of abstract)
Agent: Shumaker & Sieffert, P. A. - St. Paul, MN, US Inventor: Robert W. Dixon USPTO Applicaton #: 20060112252 - Class: 711170000 (USPTO) Related Patent Categories: Electrical Computers And Digital Processing Systems: Memory, Storage Accessing And Control, Memory Configuring The Patent Description & Claims data below is from USPTO Patent Application 20060112252. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] This application relates generally to memory caching in a peripheral device and more particularly to a method and apparatus for using a portion of a memory space of a host computer as additional cache memory for a peripheral device. BACKGROUND OF THE INVENTION [0002] The performance of a peripheral device that has a memory cache can be substantially increased when the size of the memory cache is increased. However, increasing the size of the memory cache of a peripheral device can be prohibitively expensive. Consequently, peripheral devices have limited cache capability built into them. This limited cache memory potentially provides a substantial burden on the throughput that the host and the peripheral device are able to handle, and thus achievable performance of the peripheral device in operation is a compromise of performance and cost. [0003] Accordingly there is a need for effectively increasing the buffer memory of a peripheral device without additional cost. The present invention provides a solution to this and other problems, and offers other advantages over the prior art. SUMMARY OF THE INVENTION [0004] Against this backdrop the present invention has been developed. In embodiments of the present invention, the effective size of the memory cache of a peripheral device is virtually increased by allocating unused, available memory space in a host computer to use by the peripheral device cache. According to one example, a method and apparatus is provided for virtually increasing the size of the memory cache of a peripheral device by ascertaining if there is memory space available in a connected host. In this case, the host allocates a portion of a memory space of the host for use as additional cache memory for the peripheral device. The host may provide the peripheral device with the location of the additional memory as well. The peripheral device itself may manage the additional cache memory, and preferably transfers data to and from the additional cache memory via first-party direct memory access. [0005] These and various other features as well as advantages which characterize the present invention will be apparent from a reading of the following detailed description and a review of the associated drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0006] FIG. 1 illustrates an exemplary disc drive. [0007] FIG. 2 illustrates an exemplary process for virtually increasing the size of a memory cache of a peripheral device in accordance with an embodiment of the present invention. [0008] FIG. 3 illustrates an exemplary process for saving data in the additional cache memory in accordance with an embodiment of the invention. [0009] FIG. 4 illustrates an exemplary process for retrieving data from a data storage device such as a disc drive in accordance with an embodiment of the present invention. DETAILED DESCRIPTION [0010] In an embodiment of the present invention, a portion of a memory space of a host may be used as additional cache memory for a peripheral device. One such peripheral device may be a data storage device such as a disc drive. [0011] Referring now to FIG. 1, shown therein is a functional block diagram of a disc drive 100, generally showing the main functional circuits which are resident on the disc drive printed circuit board and used to control the operation of the disc drive 100. FIG. 1 illustrates a disc drive for exemplary purposes only; as the embodiments of the present invention can be applied to any peripheral device that has a memory cache, including a disc drive. The disc drive 100 is operably connected to a host computer or other device 140 in a conventional manner. Control communication paths are provided between the host computer 140 and a disc drive microprocessor 142, the microprocessor 142 generally providing top level communication and control for the disc drive 100 in conjunction with programming for the microprocessor 142 stored in a microprocessor memory (MEM) 143. The MEM 143 can include random access memory (RAM), read only memory (ROM) and other sources of resident memory for the microprocessor 142. [0012] The discs 108 are rotated at a constant high speed by a spindle motor control circuit 148. During a seek operation; the actuator 110 moves the heads 118 between tracks on the discs 108. A servo control circuit 150 controls the position of the heads 118. During a seek operation the microprocessor 142 receives information regarding the velocity of the head 118, and uses that information in conjunction with a velocity profile stored in memory 143 to communicate with the servo control circuit 150, thereby causing the actuator assembly 110 to be pivoted. [0013] Data is transferred between the host computer 140 or other device and the disc drive 100 by way of an interface 144, which typically includes a buffer to facilitate high-speed data transfer between the host computer 140 or other device and the disc drive 100. Data to be written to the disc drive 100 is thus passed from the host computer 140 to the interface 144 and then to a read/write channel 146, which encodes and serializes the data and provides the requisite write current signals to the heads 118. To retrieve data that has been previously stored in the disc drive 100, read signals are generated by the heads 118 and provided to the read/write channel 146, which performs decoding and error detection and correction operations and outputs the retrieved data to the interface 144 for subsequent transfer to the host computer 140 or other device. [0014] The interface 144 in embodiments of the present invention preferably includes a first-party direct memory access (FPDMA) mechanism. Serial Advanced Technology Attachment (SATA) and Institute of Electrical and Electronics Engineers (IEEE) 1394 are two examples of an interface 144 that includes an FPDMA mechanism. [0015] Direct memory access (DMA) is a method of direct communication between a peripheral and the buffer memory of a host computer. Typically, the communication between the peripheral and the host computer is controlled by a DMA controller, which is a specialized processor that transfers data between buffer memory and peripheral while allowing the central processing unit (CPU) to perform other tasks. Typically, the CPU first programs the registers associated with each channel of the DMA controller. The registers in the DMA controller are given a start address of a first buffer in buffer memory where data can be read from or written to, the length of this buffer, and the direction of the data flow. A peripheral requesting a DMA transfer first signals the DMA controller via a DMA request signal. The DMA controller, in turn, responds by returning a corresponding DMA acknowledge signal. [0016] The DMA controller then directs the transfers, asserting address and strobing lines, with the peripheral asserting or receiving data to or from buffer memory. When the length field of the buffer in the DMA controller goes to zero and there is still data to be transferred, the DMA controller sends the peripheral a signal that the buffer in buffer memory is full or empty, stopping the peripheral's activity. The DMA controller or peripheral also asserts a CPU interrupt signal. In response to the interrupt, the CPU reprograms the DMA controller, giving the DMA controller a start address of a subsequent buffer where data is to be read from or written to, the length of this buffer, and the direction of the data flow. After the DMA controller has been reprogrammed, data transfer resumes. [0017] FPDMA is an alternative method for DMA in which the peripheral device is a bus master. The peripheral device may have address and control lines that connect the peripheral to the buffer memory or there may be other methods to allow the peripheral device to program the host DMA controller. The address and control lines or other method allow the peripheral device to access information regarding the location of buffers that need to be read or written to without interrupting the CPU. FPDMA allows the peripheral device to access the buffer memory of the host computer under the control of the peripheral device itself. Hardware in the host computer 140 may be configured to allow data to be sent into the memory space of the host computer 140 via FPDMA. [0018] The buffer in interface 144 is a memory cache. Whenever data is accessed from the disc, the data requested, and additional adjacent data, is stored in the memory cache. ROM in MEM 143 may include code in a module for performing certain acts of the peripheral device in accordance with the present invention, and the host computer 140 preferably includes a driver that includes code for performing certain acts of the host computer 140 in accordance with the present invention. [0019] FIG. 2 illustrates an exemplary process 200 that may be provided, for example, in such a code module, for virtually increasing the size of a memory cache of a peripheral device such as disc drive 100. Process 200 is preferably incorporated into a software module in the ROM 143 of the peripheral device and includes start block 202, block 204, decision block 206, block 208, block 210, block 212, and end block 214. Continue reading... Full patent description for Device-managed host buffer Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Device-managed host buffer patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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