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Device for avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit

Device for avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit description/claims

1. Field of the Invention

The present invention is directed to the design and manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention is directed to a method and computer program for placing fill wires in an integrated circuit design.

2. Description of Related Art

In recent semiconductor manufacturing technology, copper wires or traces are typically used to conduct signals within each net in an integrated circuit die. As the net density increases, process restrictions are imposed on the metal to oxide ratio and the uniformity of distribution of the copper metal on the surface of the die. These process restrictions are a consequence of forming the metal traces on the die. The metal traces are made by cutting trenches into a surface oxide layer of the die, filling the trenches and the die surface with copper metal, and polishing the surface of the die to just below the top of the trenches. The copper-filled trenches constitute the traces that interconnect the cells of each net.

The rate of material removal during the polishing process is dependent on the metal density, that is, the ratio of copper to oxide on the surface of the die. If the metal density is not uniform across the die, then the traces will be thinner in the high density areas than in the low density areas. The varying trace thickness presents problems in net timing modeling and may result in performance failures in the manufactured die. To maintain a uniform trench height and corresponding trace thickness, the distribution of copper metal across the surface of the die must be kept uniform within a controlled tolerance.

In one aspect of the present invention, a method of avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit die includes steps of:

receiving as input timing information for an integrated circuit design including at least one metal layer and a plurality of signal wires and dummy metal wires in the metal layer;

finding at least one of a setup time and a hold time for each signal wire in the metal layer from the timing information;

identifying a timing-critical signal wire from at least one of the setup time and the hold time for one of the signal wires that would produce a timing violation in the signal wire when the signal wire is shorted to a dummy metal wire by a process defect in the metal layer;

calculating at least one of a wire width, a fracture interval, and a spacing for modifying the dummy metal wire to avoid the timing violation in the timing-critical signal wire; and

generating as output at least one of the wire width and the fracture interval for the dummy metal wire.

In another aspect of the present invention, a computer readable storage medium tangibly embodies instructions that when executed by a computer implement a method for avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit, the method including steps of:

receiving as input timing information for an integrated circuit design including at least one metal layer and a plurality of signal wires and dummy metal wires in the metal layer;

finding at least one of a setup time and a hold time for each signal wire in the metal layer from the timing information;

identifying a timing-critical signal wire from at least one of the setup time and the hold time for one of the signal wires that would produce a timing violation in the signal wire when the signal wire is shorted to a dummy metal wire by a process defect in the metal layer;

calculating at least one of a wire width, a fracture interval, and a spacing for modifying the dummy metal wire to avoid the timing violation in the timing-critical signal wire; and

generating as output at least one of the wire width and the fracture interval for the dummy metal wire.

The term “firmware” is used herein to mean “a computer readable storage medium tangibly embodying instructions that when executed by a computer implement a method”.

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