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Device containing isolation regions with threading dislocationsRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Including Semiconductor Material Other Than Silicon Or Gallium Arsenide (gaas) (e.g., Pb X Sn 1-x Te), Containing Germanium, GeDevice containing isolation regions with threading dislocations description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070018285, Device containing isolation regions with threading dislocations. Brief Patent Description - Full Patent Description - Patent Application Claims
REFERENCE TO RELATED APPLICATIONS [0001] This Application is a divisional of and claims priority to U.S. patent application Ser. No. 11/187,444 filed on Jul. 22, 2005 entitled METHOD FOR CONTROLLING DISLOCATION POSITIONS IN SILICON GERMANIUM BUFFER LAYERS. Priority is claimed under 35 U.S.C. .sctn..sctn. 102 and 121. U.S. patent application Ser. No. 11/187,444 is incorporated by reference as if set forth fully herein. TECHNICAL FIELD [0002] The disclosure generally relates methods for controlling dislocation positions in buffer layers, such as for semiconductors, such as silicon or silicon germanium buffer layers. The disclosure further relates to methods for reducing threading dislocation density in substrates formed from semiconductors, such as for silicon-based or silicon germanium-based devices. BACKGROUND [0003] Semiconductor materials, such as silicon germanium (SiGe) and strained silicon (Si) based devices, for example, have increasingly gained attention as candidates for next generation semiconductor devices. SiGe and Si based devices are of interest in addressing issues associated with current semiconductor devices which use a silicon channel layer disposed on a silicon substrate, for example. SiGe and Si based channel devices have the potential to be used in high speed devices with potentially higher carrier mobility than current silicon channel devices. [0004] SiGe channels typically are difficult to grow on silicon substrates because of the large lattice constant mismatch between silicon and germanium. Consequently, current methods employ a quality relaxed silicon germanium intermediate layer or "virtual substrate" to provide a lattice constant that is larger than the underlying silicon substrate (e.g., substrate). For example, a thin Si epitaxial layer under tensile strain may be grown on top of the "virtual substrate" to be used as the MOSFET channel. [0005] In current applications, for example, a silicon germanium buffer layer may be grown on a silicon substrate by heteroepitaxy through molecular beam epitaxy or chemical vapor deposition (CVD). The growth condition may be such that the silicon germanium buffer layer is in a state of near complete strain relaxation throughout the growth process leading to a larger in-plane lattice constant on its surface than the silicon substrate. The increased lattice constant may be the result of "misfit dislocations" formed in the relaxed silicon germanium layer. At typical temperatures of epitaxial growth and relaxation, such dislocations may comprise 60-degree type dislocations that move in (111) planes, for example. [0006] Generally, during the relaxation process, only the misfit segments of the dislocation half-loops contribute to the relaxing of the in-plane strain. Consequently, the misfit segments (as opposed, for example, to threading dislocations) are typically desirable for relaxed buffer layers. The threading arms associated with each dislocation half-loop are, however, undesirable. The goal of relaxed SiGe buffer layer fabrication methods is to thus maximize ratio of misfit to threading dislocation density. Moreover, a flat surface is desirable to reduce interface scattering associated with undulation of the substrate interface. [0007] Use of graded silicon germanium buffer layers has been investigated as one potential approach to obtain a quality silicon germanium virtual substrate. Generally, this involves a SiGe buffer layer with a continuously graded amount of Ge in the SiGe buffer layer. In the case of a SiGe layer with a constant composition (i.e., not graded) grown on a silicon substrate, for example, dislocations may nucleate during growth and interact with one another. This interaction inhibits dislocations from propagating to the substrate edge and may leave a large number of threading arms on the surface of the SiGe layer. [0008] In contrast, if a graded Ge composition is used, during relaxation of the SiGe layer on the silicon substrate, the nucleation of dislocations across the surface may be mitigated by reducing the strain accumulation rate. Consequently, the interaction between dislocations may be reduced and the density of threading arm dislocations on the surface of the SiGe layer may be reduced. For instance, for a constant SiGe layer grown directly on a silicon substrate, the density of threading dislocations may be around 10.sup.8.about.9 /cm.sup.2. In contrast, the density of threading dislocations in a graded SiGe layer grown on a silicon substrate may be around 10.sup.4.about.5 /cm.sup.2. While graded SiGe reduces the threading dislocation density, the Ge grading rate may be low, typically at or less than 10%/.mu.m. Consequently, this requires a large thickness of graded SiGe buffer layer, which is a drawback because of, among other reasons, the increased production costs and increased thermal resistance. The thick graded SiGe buffer layer thus reduces the number of practical applications in which SiGe based devices can be used. Moreover, the strain-relaxed graded SiGe buffer layer generally has a rough surface. [0009] One approach to reducing the threading dislocation density includes employing a low temperature silicon buffer layer prior to growing a silicon germanium layer. In addition, ion implantation after growing a strained SiGe layer and subsequent annealing has been investigated as a potential solution to reducing threading dislocation density. Generally, these methods function by introducing non-equilibrium point defects in the layers through a low temperature silicon buffer layer or through ion implantation and then inducing the clustering of point defects to relax the strain. This results in a low density of threading dislocations. These approaches have shown reduced threading density values of less than 10.sup.4/cm.sup.2. [0010] The above-identified proposed solutions have demonstrated SiGe buffer layers with reduced threading dislocation density compared to the constant composition SiGe layer directly grown on silicon substrate. However, the density of threading dislocation is still higher than about 1/cm.sup.2 if the buffer layer is grown on a silicon substrate. Moreover, threading dislocations may be randomly distributed across the entire substrate. This random distribution of threading dislocations may result in deviation of the properties of individual devices formed on the substrate. In other words, threading dislocations degrade some devices formed on the surface of the substrate while others are not. [0011] Ideally, a relaxed SiGe buffer layer has no threading dislocations on the entire or a significant portion of the surface. However, from a device fabrication point of view, it is not necessary for the entire surface of the substrate to be free of threading dislocations. For example, in current semiconductor designs, individual devices may be fabricated on a substrate and are separated by non-functional field oxide or trench isolation regions. These regions may be employed to separate adjacent devices. Thus, it may be possible to achieve suitable conditions by removing the threading dislocations from the areas of the surface in which or on which devices are to be built. Consequently, it is desirable to form a relaxed SiGe layer without threading dislocations at position-controlled regions where the devices are built. [0012] Attempts have been made to control the location of dislocation distribution by forming patterned silicon mesa structures with and without Ge implantation. For example, Fitzgerald et al., Elimination of Dislocations in Heteroepitaxial MBE and RTCVD Ge.sub.xSi.sub.1-x Grown on Patterned Si Substrates, J. Electronic Materials, 19, 949 (1990) describes a process of fabricating a patterned silicon mesa structure and then growing a SiGe layer thereon. The patterned mesa structure reduces the threading dislocation density by limiting the dislocation interaction at small growth areas and then allowing the threading segments to escape at the mesa edge. [0013] In Watson et al., Influence of Misfit Dislocation Interactions on Photoluminescence Spectra of SiGe on patterned Si, J. Appl. Phys. 83, 3773 (1998), discloses a process of controlling dislocation nucleation during SiGe layer growth on Ge implanted Si regions that were previously patterned before implantation. However, the use of mesa structures raises complications because the non-planar mesa structure is fundamentally incompatible with planar silicon VLSI technology. SUMMARY [0014] A method is disclosed for forming dislocations in selected areas or regions of a planar strained silicon germanium layer grown on a silicon substrate. The method may also be used for forming dislocations in selected areas or regions of a planar silicon substrate. In one aspect of the method, dislocations may be formed by intentionally damaging selected regions through ion implantation, ion beam illumination, or other energetic beam illumination. [0015] The damaged regions may contain a plurality of dislocation half-loops or full loops. After an annealing process, the dislocations relax the strain of the silicon germanium layer by permitting the misfit segments to propagate from one damaged region to another. In the damaged region, the dislocation density may be extremely high leading to extensive dislocation-dislocation interaction. The dislocation half-loops with the correct Burger's vectors at the outskirts of the damaged regions may be free to move out into the strained film upon annealing. The net result is that the damaged regions may act as sources as well as barriers/sinks for dislocation half-loops. [0016] In one embodiment, the method may form dislocations and in particular, threading dislocations, in the damaged or ion implanted regions of a substrate or overlying SiGe layer. In one aspect the locations of the threading dislocations may be lithographically defined. [0017] While the method may produce substrates having average threading density values greater than conventional relaxed buffer layers (as measured across the entire substrate surface), the density may be concentrated in one or more regions that are not used to create active electronic devices. The threading dislocation density in these "pristine" or undamaged regions may be as low as the starting silicon wafers. The damaged regions where dislocations may be preferentially formed may be used for trench isolation regions or field oxide regions, thereby reducing any potential to waste areas of the substrate. [0018] The overall fraction of the damaged regions using this method may be estimated as follows. The width of the damaged region may be defined using conventional lithographic techniques to be as narrow as 0.1 .mu.m. A separation between the damaged regions may be dictated by an average misfit dislocation lengths, which may be on the order of 50 .mu.m or larger. As a result, the fractional area occupied by the damaged regions may be less than 1%. [0019] In one aspect of the process, threading arms may be located at one or more "damaged" regions, leaving the remainder of the substrate (or overlying layer) with substantially no threading dislocations. The damaged regions may occupy a small fraction of the overall surface area of the substrate. The damaged regions may be formed into field oxides or trenches for isolation between devices, thereby avoiding waste of the surface area of the substrate. [0020] In another embodiment, a thin silicon layer may be grown over the silicon germanium layer as a nucleation-inhibiting layer. The silicon "capping" layer may prevent nucleation of dislocation loops at a free surface of the SiGe layer. The process may also be optimized with respect to other parameters such as growth temperature, thickness, Ge composition of the SiGe layer, and annealing conditions to prevent unwanted nucleation of dislocations in the non-damaged regions of the substrate. Continue reading about Device containing isolation regions with threading dislocations... Full patent description for Device containing isolation regions with threading dislocations Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Device containing isolation regions with threading dislocations patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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