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  Design pattern correcting method, design pattern forming method, process proximity effect correcting method, semiconductor device and design pattern correcting programUSPTO Application #: 20050251781Title: Design pattern correcting method, design pattern forming method, process proximity effect correcting method, semiconductor device and design pattern correcting program Abstract: A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other. (end of abstract)
Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP - Washington, DC, US Inventors: Toshiya Kotani, Shigeki Nojima, Shimon Maeda USPTO Applicaton #: 20050251781 - Class: 716019000 (USPTO) Related Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Design Of Semiconductor Mask The Patent Description & Claims data below is from USPTO Patent Application 20050251781. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2004-134011, filed Apr. 28, 2004, the entire contents of which are incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a design pattern correcting method for correcting a design pattern, a design pattern forming method for forming a design pattern based on a design rule, a process proximity effect correcting method for, when forming a desired pattern planar shape on a wafer using a design pattern, implementing a processing for proximity effect correction, a semiconductor device and a design pattern correcting program. [0004] 2. Description of the Related Art [0005] In recent years, progress of semiconductor manufacturing technology is very remarkable and semiconductors whose minimum design rule is 0.18 .mu.m have been mass-produced. Such miniaturization has been achieved by remarkable progresses of such fine pattern forming technology as mask process technology, lithography process technology and etching process technology. [0006] At a time when the pattern size was sufficiently large, a mask pattern having the same shape as a pattern written by a designer was formed and the mask pattern was transferred to resist coated on a wafer with a photolithography machine, thereby forming the designed mask pattern. However, influence made by refraction of exposure light upon the dimension of the wafer has been increased by the miniaturization of the pattern size, and the process technology for the mask and wafer for forming such a fine pattern accurately has become difficult. Therefore, it has been difficult to form a pattern just the same as a designed one on a wafer even if the same mask as the design pattern is employed. [0007] In order to improve the correspondence of the design pattern, technologies called optical proximity correction (OPC) for implementing a predetermined correction and process proximity correction (PPC) have been used for a mask pattern for forming the same pattern as the design pattern on the wafer. [0008] The OPC technology and PPC technology (hereinafter expressed as PPC including OPC) are classified largely to two methods. According to one of them, a moving amount of an edge constituting a design pattern corresponding to the width of the design pattern or a most proximate distance between the patterns is specified as a rule, and the edge is moved following the rule. A second method is to optimize an edge moving amount such that the same pattern as the design pattern can be formed on the wafer by using a lithography simulator capable of estimating the diffracted light intensity distribution of exposure light. Further, a correcting method capable of achieving a higher precision correction by combining these two methods has been proposed (for example, Jpn. Pat. Appln. KOKAI Publication No. 2002-258459). [0009] Generally, the PPC method using the lithography simulator is called model base PPC. According to this method, by comparing an optical image calculated from a model with a design pattern, the edge of the pattern is moved corresponding to the comparison result. At that time, the design pattern needs to be divided to edge groups of a certain unit, and an appropriate correction value is calculated for each edge. With miniaturization of lithography intensified, the resolution of the pattern on the wafer has been deteriorated more and more, and particularly, deterioration (meaning that the shape of the pattern cannot be formed on the wafer just as the design pattern indicates) of the resolution at a corner portion of the pattern is remarkable. [0010] Therefore, when the pattern is divided to edge groups, usually the corner portion of the pattern in which the deterioration of the resolution is particularly serious is preferentially divided. Consequently, such an edge division that the corner portion of the pattern is optimized is achieved, so that the shape of the corner portion in which the deterioration of the resolution is serious can be optimally corrected. [0011] However, examples of the design pattern include a design pattern having a small step in the vicinity of a corner portion thereof. In the case of setting a design rule of the layout or using an automatic layout design tool indispensable for designing a large-scale device, generation of the step in the vicinity of the pattern corner portion is an unavoidable problem. Because the edge division is started from the corner portion of the pattern as described above, even a minute step is recognized as a corner portion. As a result, predetermined edge division cannot be performed between an original corner portion and the minute step, and consequently, the correction is not carried out in a predetermined manner at the corner portion in which the deterioration of the resolution is serious, so that a problem may occur in mask formation or the configuration of the wafer. [0012] In such a pattern having a small step in the vicinity of a corner portion thereof, conventionally, it is difficult to finish the corner portion into a desired pattern and this is a main cause which deteriorates pattern accuracy. BRIEF SUMMARY OF THE INVENTION [0013] According to a first aspect of the present invention, there is provided a design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, comprising: [0014] extracting at least one of two edges extended from a vertex of the design pattern; [0015] measuring a length of the extracted edge; [0016] determining whether or not the length of the measured edge is shorter than a predetermined value; [0017] extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value; and [0018] reshaping the design pattern to match positions of the two extracted vertexes with each other. [0019] According to a second aspect of the present invention, there is provided a design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, comprising: [0020] extracting an edge extended from a vertex of the design pattern; [0021] measuring a length of the extracted edge; Continue reading... Full patent description for Design pattern correcting method, design pattern forming method, process proximity effect correcting method, semiconductor device and design pattern correcting program Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Design pattern correcting method, design pattern forming method, process proximity effect correcting method, semiconductor device and design pattern correcting program patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. 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