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  Deposition of silicon germanium on silicon-on-insulator structures and bulk substratesUSPTO Application #: 20070042572Title: Deposition of silicon germanium on silicon-on-insulator structures and bulk substrates Abstract: Methods are provided for producing SiGe-on-insulator structures and for forming strain-relaxed SiGe layers on silicon while minimizing defects. Amorphous SiGe layers are deposited by CVD from trisilane and GeH4. The amorphous SiGe layers are recrystallized over silicon by melt or solid phase epitaxy (SPE) processes. The melt processes preferably also cause diffusion of germanium to dilute the overall germanium content and essentially consume the silicon overlying the insulator. The SPE process can be conducted with or without diffusion of germanium into the underlying silicon, and so is applicable to SOI as well as conventional semiconductor substrates. (end of abstract) Agent: Knobbe Martens Olson & Bear LLP - Irvine, CA, US Inventor: Matthias Bauer USPTO Applicaton #: 20070042572 - Class: 438478000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Formation Of Semiconductive Active Region On Any Substrate (e.g., Fluid Growth, Deposition) The Patent Description & Claims data below is from USPTO Patent Application 20070042572. Brief Patent Description - Full Patent Description - Patent Application Claims
PRIORITY APPLICATION [0001] This application claims the benefit of U.S. Provisional Patent Application 60/489,691, filed 23 Jul. 2003, the entire disclosure of which is hereby incorporated by reference herein. FIELD OF THE INVENTION [0002] The present invention relates generally to strained silicon on strain relaxed silicon germanium, including silicon-germanium-on-insulator ("SGOI") technology in integrated circuit fabrication. BACKGROUND OF THE INVENTION [0003] To improve device performance, a trend is developing for replacing conventional "bulk" silicon wafers with so-called silicon-on-insulator ("SOI") wafers. The advantage of SOI technology is that the silicon in which transistors are made is not in electrical contact with the remainder of the wafer, such that no cross-talk among transistors takes place through the wafer bulk. The transistors are more effectively electrically isolated from one another. [0004] SOI technology typically employs a thin (e.g., about 100 nm) insulating layer between the active semiconductor layer and the wafer, across the entire wafer or at least in those areas where active devices will be formed in the semiconductor layer. Silicon oxide, silicon nitride, or a combination of the two are typically employed as the insulating layer. These materials are amorphous, have excellent electrical properties, and the technology for integrating silicon nitride and/or silicon oxide is very well developed. [0005] Two conventional technologies have been developed forming the SOI structures. One technology, known as SIMOX, starts with a semiconductor structure such as a silicon wafer and employs high energy implantation of oxygen atoms to form an oxide layer greater than about 100 nm below the surface of the silicon wafer. High temperature annealing then forms a buried silicon oxide, and at the same time repairs crystal defects in the surface silicon that are created by implantation. The surface silicon remains a semiconductor material, and the crystal structure thereof is restored by the annealing process. These steps are rather expensive, however, and the quality of the insulating layer and the active silicon thereover is somewhat compromised. [0006] Another method for forming SOI structures is based on bonding a sacrificial silicon wafer onto an oxidized silicon wafer. By grinding or other thinning process, the sacrificial silicon wafer is reduced to a very thin, active semiconductor layer over the oxide from the other substrate. The thinning process, however, is critical to achieving high quality in the SOI structure, since the ultimately desired thickness uniformity of the active semiconductor layer is about 5 nm.+-.0.1 nm. Furthermore, the bonding and thinning processes are complicated and rather expensive. [0007] Strained silicon is utilized to increase carrier mobility and thus the operating speed of transistors. Typically a thin layer of silicon germanium (SiGe) is formed on a substrate and a very thin layer of silicon is deposited over the SiGe. Silicon has a smaller lattice constant than germanium, and when the silicon layer is grown on relaxed SiGe, the silicon atoms tend to align themselves with the more widely spaced atoms in the underlying layer. As a result, the top silicon layer is stretched, or strained, allowing electrical carriers to flow with less resistance. [0008] Strained silicon and SOI are complementary technologies and several attempts have been made to fabricate SiGe-On-Insulator (SGOI) substrates. SUMMARY OF THE INVENTION [0009] In accordance with one aspect of the invention, a method for forming a strained silicon on strain relaxed SiGe-on-insulator structure includes forming an amorphous SiGe layer on an SOI substrate by CVD and annealing the substrate at a temperature that causes the SiGe layer to melt. Ge from the SiGe layer diffuses into the underlying Si layer at the annealing temperature, producing a relaxed SiGe layer over an oxide. [0010] In accordance with another aspect of the invention, a method for forming a strain-relaxed SiGe layer on a substrate comprises depositing an amorphous SiGe layer over a silicon layer by CVD using trisilane as a precursor. Solid phase epitaxy is conducted to crystallize the SiGe layer over the silicon layer. Prior to depositing the amorphous SiGe layer, the silicon layer is covered with less than one monolayer of oxide, leaving some crystal silicon regions exposed. [0011] In a further aspect of the invention, a method for forming a strain relaxed SiGe layer over a silicon layer on a substrate comprises heteroepitaxy of SiGe at low temperature. Preferably the strained SiGe layer is deposited by CVD from trisilane and a germanium precursor. A bubble forming agent, such as H or He is implanted at or below the Si/SiGe interface and the SiGe layer is annealed. During annealing the SiGe layer relaxes. A strained silicon layer can subsequently be deposited over the relaxed SiGe layer. BRIEF DESCRIPTION OF THE DRAWINGS [0012] These and other aspects of the invention will be readily apparent from the detailed description below and from the appended drawings, which are meant to illustrate and not to limit the invention, and in which: [0013] FIG. 1 is a schematic cross section showing deposition of an amorphous silicon germanium (.alpha.-SiGe) layer over a silicon-on-insulator (SOI) wafer. [0014] FIG. 2 illustrates deposition of an amorphous silicon (.alpha.Si) layer over the .alpha.-SiGe layer of FIG. 1. [0015] FIG. 3 illustrates formation of a silicon oxide over the .alpha.-SiGe layer of FIG. 1, either by oxidation of the .alpha.-Si layer of FIG. 2 or by separate deposition of SiO2 over the .alpha.-SiGe layer of FIG. 1. [0016] FIG. 4 illustrates a melting/diffusion process in accordance with a preferred embodiment of the present invention. [0017] FIG. 5 illustrates a relaxed SiGe layer as a result of the melting/diffusion process. [0018] FIG. 6 is a chart illustrating crystallization rates of solid phase epitaxy, for various different concentrations of germanium in the SiGe layer. [0019] FIG. 7 illustrates defect density versus germanium content using conventional epitaxy and formation of the relaxed SiGe layer in accordance with the preferred embodiments. Continue reading... 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