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  Delegating tasks between multiple processor coresRelated Patent Categories: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors), Processing Control, Context Preserving (e.g., Context Swapping, Checkpointing, Register WindowingDelegating tasks between multiple processor cores description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060026407, Delegating tasks between multiple processor cores. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application claims priority to European Patent Application No. 04291918.3, filed on Jul. 27, 2004 and incorporated herein by reference. This application is related to co-pending and commonly assigned applications Ser. No. ______ (Attorney Docket No. TI-38581 (1962-22200)), entitled, "Emulating A Direct Memory Access Controller," and Ser. No. ______ (Attorney Docket No. TI-38584 (1962-22500), entitled, "Interrupt Management In Dual Core Processors," which are incorporated by reference herein. BACKGROUND [0002] Many systems comprise dual processor cores. One of these processor cores is typically designated to be the "host," or main, processor. The other processor may be termed a "secondary" processor. While performing a series of tasks, the host processor may determine that delegating one or more tasks to the secondary processor would be expeditious, so that the host processor may allocate its resources for performing other tasks. In such a case, the host processor must program the secondary processor to perform the task or tasks that are to be delegated. For example, if the host processor delegates the execution of a particular algorithm to the secondary processor, the host processor must program the secondary processor to execute the algorithm. It is time-consuming and energy-consuming for a host processor to have to program the secondary processor. BRIEF SUMMARY [0003] Disclosed herein is a technique for delegating tasks between multiple processor cores. An illustrative embodiment comprises an electronic device comprising a first processor and a second processor, the second processor coupled to the first processor and adapted to receive an address from the first processor, to pause execution of a first thread at a switch point, and to use the address to retrieve and execute a group of instructions in a second thread. Prior to executing the group of instructions in the second thread, the second processor pushes onto a hardware-controlled stack data pertaining to the switch point, the data comprising information needed to resume execution of the first thread at the switch point. [0004] Another illustrative embodiment comprises a processor that comprises decode logic adapted to receive from another processor an address of a group of instructions. The processor also comprises fetch logic coupled to the decode logic and adapted to fetch the group of instructions from storage. The decode logic pauses processing of a first thread at a switch point and processes the group of instructions in a separate thread. Prior to processing the group of instructions, the processor pushes onto a hardware-controlled stack data pertaining to the switch point, the data comprising contents of registers used by the group of instructions. [0005] Yet another illustrative embodiment comprises a method of delegating a task from a first processor to a second processor. The method comprises transferring an address of a group of instructions from the first processor to the second processor, pausing execution of a first thread in the second processor at a switch point, pushing data onto a stack, the data comprising contents of registers used by the group of instructions. The method further comprises retrieving the group of instructions using the address, executing the group of instructions in a second thread, and popping the data off of the stack and storing the data to the registers in the second processor. NOTATION AND NOMENCLATURE [0006] Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms "including" and "comprising" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to . . . ". Also, the term "couple" or "couples" is intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections. BRIEF DESCRIPTION OF THE DRAWINGS [0007] For a more detailed description of the preferred embodiments of the present invention, reference will now be made to the accompanying drawings, wherein: [0008] FIG. 1 shows a diagram of a system in accordance with preferred embodiments of the invention and including a Java Stack Machine ("JSM") and a Main Processor Unit ("MPU"), in accordance with embodiments of the invention; [0009] FIG. 2 shows a block diagram of the JSM of FIG. 1 in accordance with preferred embodiments of the invention; [0010] FIG. 3 shows various registers used in the JSM of FIGS. 1 and 2, in accordance with embodiments of the invention; [0011] FIG. 4 shows the preferred operation of the JSM to include "micro-sequences," in accordance with embodiments of the invention; [0012] FIG. 5 shows an illustrative switching process between two execution threads, in accordance with a preferred embodiment of the invention; [0013] FIG. 6 shows an illustrative 32-bit instruction that may be incorporated into a micro-sequence, in accordance with a preferred embodiment of the invention; [0014] FIG. 7 shows a flow diagram of the switching process of FIG. 5, in accordance with embodiments of the invention; [0015] FIG. 8 shows a flow diagram describing a delegation technique in accordance with a preferred embodiment of the invention; and [0016] FIG. 9 shows the system described herein, in accordance with preferred embodiments of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0017] The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims, unless otherwise specified. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment. [0018] Described herein is a technique by which a host processor may delegate a task to a secondary processor by simply sending a command and an address to the secondary processor. The command causes the secondary processor to use the address to locate and retrieve a group of instructions that has been pre-programmed into the secondary processor. Executing this group of instructions causes the secondary processor to perform whatever task the host processor delegated to the secondary processor. However, before the secondary processor executes the group of instructions, it must first stop what it is doing in a currently executing thread and must further "bookmark" its place in the currently executing thread. By bookmarking its place in the currently executing thread, the secondary processor can execute the group of instructions and then resume executing in the thread at the bookmarked location. Accordingly, a technique for bookmarking a spot in a thread and a technique for delegating tasks from the host processor to the secondary processor are now discussed in turn. Continue reading about Delegating tasks between multiple processor cores... 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