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  Delay test method for large-scale integrated circuitsRelated Patent Categories: Error Detection/correction And Fault Detection/recovery, Pulse Or Data Error Handling, Digital Logic Testing, Scan Path Testing (e.g., Level Sensitive Scan Design (lssd))Delay test method for large-scale integrated circuits description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060236179, Delay test method for large-scale integrated circuits. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a method of testing a large-scale integrated (LSI) circuit with a built-in scan test function, to detect delay faults. [0003] 2. Description of the Related Art [0004] Part of an LSI circuit with a built-in scan test function is illustrated schematically in FIG. 1. Combinatorial circuits 1A and 1B are linked through scan flip-flops (S-FF) 2B.sub.1, 2B.sub.2, . . . , 2B.sub.m, which are interconnected to form a scan chain 2B. Each scan flip-flop includes a selector 7 controlled by a scan enable signal SE to select an input signal and a flip-flop 8 that latches the selected signal in synchronization with a clock signal CKB and outputs the latched signal. [0005] Signals output in parallel from combinatorial circuit 1A are supplied to the first inputs of the selectors 7 in the scan flip-flops 2B.sub.1, 2B.sub.2, . . . , 2B.sub.m, and the signals output from the flip-flops 8 are supplied in parallel to the input side of combinatorial circuit 1B. The output of the flip-flop 8 in each of the first m-1 scan flip-flops 2B.sub.1, 2B.sub.2, . . . , 2B.sub.m is also connected to the second input of the selector 7 in the next scan flip-flop 2B.sub.2, 2B.sub.3, . . . , 2B.sub.m. The second input of the selector 7 in the first scan flip-flop 2B.sub.1 in the chain is connected to a scan input terminal 3B, and the output of the flip-flop 8 in the last scan flip-flop 2B.sub.m in the chain is connected to a scan output terminal 4B. [0006] Signals from another chain 2A of scan flip-flops 2A.sub.1, 2A.sub.2, . . . , 2A.sub.k are supplied in parallel to the input side of combinatorial circuit 1A. The second input of the selector 7 in scan flip-flop 2A.sub.1 is connected to a scan input terminal 3A; the output of the flip-flop 8 in scan flip-flop 2A.sub.k is connected to a scan output terminal 4A. [0007] A third chain 2C of scan flip-flops 2C.sub.1, 2C.sub.2, . . . , 2C.sub.n is connected to the output side of combinatorial circuit 1B. The second input of the selector 7 in scan flip-flop 2C.sub.1 is connected to a scan input terminal 3C; the output of the flip-flop 8 in scan flip-flop 2C.sub.n is connected to a scan output terminal 4C. [0008] A clock signal CLK is supplied from a clock terminal 5 to the clock input terminal of the flip-flop 8 in each scan flip-flop via a clock distribution circuit or clock tree. The scan enable signal SE is supplied to the control terminal of the selector 7 in each scan flip-flop from a scan enable terminal 6. [0009] A conventional delay test of combinatorial circuit 1B in FIG. 1 is conducted as illustrated by the signal waveform diagram in FIG. 2. It is assumed that combinatorial circuits 1A and 1B input and output four signals each. The delay being tested is the propagation delay D from the input of test data to the input side of combinatorial circuit 1B to the output of signals indicating the results of logic operations on the test data from the output side of combinatorial circuit 1B. The clock signal CLK supplied from the clock terminal 5 propagates as a clock signal CKB with a delay .alpha. to scan chain 2B and as a clock signal CKC with a delay .beta. to scan chain 2C. [0010] First, the scan enable signal SE is set to the high logic level, switching the selectors 7 of all scan flip-flops to the second input side. Scan flip-flops 2A.sub.1 to 2A.sub.4 thereby form a shift register extending from scan input terminal 3A to scan output terminal 4A, the signals output from the scan flip-flops 2A.sub.1 to 2A.sub.4 also being supplied in parallel to combinatorial circuit 1A. Similarly, scan flip-flops 2B.sub.1 to 2B.sub.4 form a shift register extending from scan input terminal 3B to scan output terminal 4B, the signals output from scan flip-flops 2B.sub.1 to 2B.sub.4 also being supplied in parallel to combinatorial circuit 1B. [0011] At time t1 in FIG. 2, the scan input signals SIA and SIB supplied to scan input terminals 3A and 3B are set according to test data TDA and TDB to signal levels `a4`and `b4` (where `a4`and `b4` are either the high or low logic level) and a clock pulse is supplied to the clock terminal 5. After propagation delays in the clock distribution circuitry, scan flip-flops 2A.sub.1 and 2B.sub.1 latch the data `4a` and `4b`. [0012] Next, at times t2, t3, and t4, scan input signals SIA (`a3`, `a2`, `a1`) are supplied from the scan input terminal 3A one by one and shifted into scan chain 2A in synchronization with the clock signal CLK. Scan input signals SIB (`b3`, `b2`, `b1`) are similarly shifted from scan input terminal 3B into scan chain 2B. After the above scan shift operations, test data TDA (`a1`, `a2`, `a3`, `a4`) are held in scan flip-flops 2A.sub.1 to 2A.sub.4 and supplied in parallel to combinatorial circuit 1A, while test data TDB are held in scan flip-flops 2B.sub.1 to 2B.sub.4 and supplied in parallel to combinatorial circuit 1B. Combinatorial circuit 1A performs logic operations on test data TDA and, after a certain delay, outputs resultant signal data RDA in parallel as an input test pattern. In the meantime, combinatorial circuit 1B performs logic operations on test data TDB and, after a certain delay, outputs resultant signal data RDB1 in parallel. [0013] At time t5, the scan enable signal SE at terminal 6 is driven low, switching the selectors 7 of all scan flip-flops to the first input side. The signals output from combinatorial circuit 1A are now supplied to scan chain 2B, but the data latched in scan flip-flops 2B.sub.1 to 2B.sub.4 do not immediately change, because no clock pulse is supplied to the clock terminal 5. [0014] At time t6, a launch clock pulse is supplied from the clock terminal 5, reaching scan chain 2B as clock signal CKB with a delay .alpha.. The signal data RDA output from combinatorial circuit 1A and received by scan flip-flops 2B.sub.1 to 2B.sub.4 are supplied almost simultaneously to combinatorial circuit 1B. (As the circuits distributing the clock signals to scan flip-flop 2B.sub.1 to 2B.sub.4 are not quite identical, these flip-flops do not operate with perfect simultaneity.) Combinatorial circuit 1B now performs logic operations on the newly supplied signal data RDA and, after a concomitant delay D, outputs the results RDB2 to the first inputs of the selectors 7 in scan flip-flops 2C.sub.1 to 2C.sub.4. During this delay D, the signals output from combinatorial circuit 1B switch from their old values to their new values. [0015] After a delay T from time t6, a capture clock pulse is supplied from the clock terminal 5 at time t7, reaching scan chain 2C as clock signal CKC with a delay .beta.. Scan flip-flops 2C.sub.1 to 2C.sub.4 now latch the resultant signal data RDB2 from combinatorial circuit 1B. The scan output signal SOC output from scan output terminal 4C is `c4`. [0016] At time t8, the scan enable signal SE returns to the high logic level and the selectors 7 of all scan flip-flop are switched to the second input side to resume scan shift operations. [0017] The remaining data (`c3`, `c2`, `c1`) captured in scan flip-flops 2C.sub.1 to 2C.sub.3 are then shifted one by one into scan flip-flop 2C.sub.4 in synchronization with clock signal CKC and output serially as scan output signal SOC from scan output terminal 4C at times t9 to t11 (with a delay of .beta. in each case). [0018] The propagation delay D of the logic operations performed in combinatorial circuit 1B can therefore be tested by checking the scan output signal SOC following times t7, t9, t10, and t11. If the scan output signal SOC matches the values (the output test pattern) expected to be obtained from the input data RDA by the logic operations performed in combinatorial circuit 1B, it can be concluded that the following inequality (1) is satisfied. .alpha.+D<.beta.+T (1) [0019] When the scan output signal SOC does not match the expected values, it can be concluded that the above inequality is not satisfied. This indicates that the delay D being tested has been prolonged for some reason, such as a defect introduced in the manufacturing process. [0020] A delay test of the LSI circuit in FIG. 1 is carried out using the equipment illustrated in FIG. 3. First, logic circuit information describing the combinatorial circuits of the LSI circuit to be tested is supplied to a test pattern generating device 10 (for example, a computer with a program for generating test pattern data) that can generate test patterns for a delay test, and the relevant input and output scan segments are specified. In this example, the circuit to be tested is combinatorial circuit 1B, the relevant input scan segments are the scan chains 2A and 2B on the input sides of combinatorial circuits 1A and 1B, and the relevant output scan segment is the scan chain 2C on the output side of combinatorial circuit 1B. [0021] The test pattern generating device 10 then generates test pattern data indicating the transitions over time of the signals CLK, SE, SIA, SIB, and SOC at terminals 5, 6, 3A, 3B, and 4C in the LSI circuit under test. The launch-to-capture delay T in the test pattern data is selected so that the above inequality (1) will be satisfied when the propagation delay D of combinatorial circuit 1B is within tolerance, and will not be satisfied when the propagation delay D is over tolerance. [0022] Next, the resultant test pattern data are read into the scan test device 20. The scan test device 20 has a random-access memory (RAM) 22 in which the timings of the test pattern data are mapped onto different addresses. The status (`1` or `0`) of signals CLK, SE, SIA, and SIB and the expected status of signal SOC at each timing are stored at the corresponding address. The scan test device 20 also comprises a clock generator or oscillator (OSC) 24 that generates a read clock signal CK, an address counter 26 that counts the clock signal CK to generate a memory address signal ADR, and a comparator (CMP) 28. Data read out one by one from the memory 22 according to the address signal ADR are supplied as signals CLK, SE, SIA, SIB to the corresponding terminals 5, 6, 3A and 3B of the LSI circuit under test 30. [0023] The expected SOC signal data read out from the memory 22 are supplied to one of the input terminals of the comparator and compared with the scan output signal SOC obtained from scan output terminal 4C of the circuit under test 30 (the scan output signal SOC is supplied to the other terminal of the comparator). The result of the comparison is output to indicate the test result. Continue reading about Delay test method for large-scale integrated circuits... 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