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  Delay locked loop structure providing first and second locked clock signalsDelay locked loop structure providing first and second locked clock signals description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070063748, Delay locked loop structure providing first and second locked clock signals. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND [0001] Typically, a computer system includes a number of integrated circuit chips that communicate with one another to perform system applications. As chip speeds increase, the amount of data communicated between chips increases to meet the demands of some system applications. Other system applications do not need the increased chip speeds and bandwidth or the systems have limited power resources. In these systems, the chips can operate at slower speeds and lower power levels. In other systems, applications are being developed to take advantage of a dynamic frequency change environment. In the dynamic frequency change environment, the operational frequency of at least some of the chips can be changed from one frequency to any other frequency within a specified frequency range. [0002] Often, the computer system includes a controller, such as a micro-processor, and one or more memory chips, such as random access memory (RAM) chips. The RAM chips can be any suitable type of RAM, such as dynamic RAM (DRAM), double data rate synchronous DRAM (DDR-SDRAM), graphics DDR-SDRAM (GDDR-SDRAM), reduced latency DRAM (RLDRAM), pseudo static RAM (PSRAM), and low power DDR-SDRAM (LPDDR-SDRAM). [0003] Sometimes, data and a strobe signal are communicated between chips, such as a controller and a RAM, via a communications link to read and write data. The RAM receives an external clock signal and provides an internal clock signal based on the received external clock signal. To write data from the controller to the RAM, data and a strobe signal are transmitted to the RAM and the received data is sampled via the received strobe signal. The RAM clocks the received data into the chip via the internal clock signal. To read data from the RAM, output data and strobe signals are transmitted from the RAM. The output data and strobe signals are aligned with the external clock signal via the internal clock signal. The internal clock signal can be locked to the external clock signal and track the external clock signal frequency via a delay locked loop (DLL). [0004] In a dynamic frequency change environment, the controller may slowly change the frequency of the external clock signal from one frequency to any other frequency within the frequency range of the dynamic frequency change environment. The frequency of the external clock signal gradually changes from one frequency to another frequency over many clock cycles, such as thousands of clock cycles or millions of clock cycles. [0005] Typically, a DLL in the RAM receives the external clock signal and locks onto the external clock signal to produce the internal clock signal. The internal clock signal is used internally and to provide output data and strobe signals aligned with the external clock signal. The DLL is reset to lock onto the external clock signal within a specified number of clock cycles, such as 300 or 500 clock cycles, of the external clock signal. The DLL tracks frequency changes of the external clock signal within a limited frequency range that is less than the frequency range of the dynamic frequency change environment. However, the DLL must be reset to lock onto the external clock signal beyond the limited frequency range. Resetting the DLL and locking onto the external clock signal disrupts operation of the RAM and the system. [0006] For these and other reasons there is a need for the present invention. SUMMARY [0007] One aspect of the present invention provides a delay locked loop including a first circuit and a second circuit. The first circuit is configured to receive a clock signal having a frequency and to lock onto the clock signal and provide a first locked clock signal over a first frequency range and a second locked clock signal over a second frequency range. The second circuit is configured to signal the first circuit to lock onto the clock signal to provide the second locked clock signal as the frequency changes from the first frequency range to the second frequency range. Also, the second circuit is configured to signal the first circuit to provide a locked one of the first locked clock signal and the second locked clock signal in a locked output clock signal. BRIEF DESCRIPTION OF THE DRAWINGS [0008] Embodiments of the invention are better understood with reference to the following drawings. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. [0009] FIG. 1 is a block diagram illustrating one embodiment of a computer system according to the present invention. [0010] FIG. 2 is a diagram illustrating one embodiment of a random access memory cell in the array of memory cells. [0011] FIG. 3 is a diagram illustrating one embodiment of a DLL structure and a forward path. [0012] FIG. 4 is a diagram illustrating one embodiment of an overflow and underflow detection scheme in a DLL circuit. [0013] FIG. 5 is a timing diagram illustrating the operation of one embodiment of a DLL structure. DETAILED DESCRIPTION [0014] In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as "top," "bottom," "front," "back," "leading," "trailing," etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. [0015] FIG. 1 is a block diagram illustrating one embodiment of a computer system 30 according to the present invention. Computer system 30 includes a controller 32 and a RAM 34. Controller 32 is electrically coupled to RAM 34 via memory communications path 36 and data communications path 38. Controller 32 provides row and column addresses and control signals to RAM 34 via memory communications path 36. Controller 32 provides data and strobe signals to RAM 34 and receives data and strobe signals from RAM 34 via data communications path 38. RAM 34 can be any suitable type of RAM, such as a DRAM, DDR-SDRAM, GDDR-SDRAM, RLDRAM, PSRAM, and a LPDDR-SDRAM. [0016] In other embodiments, controller 32 provides data to RAM 34 and receives data from RAM 34 via data communications path 38, wherein controller 32 and RAM 34 do not exchange strobe signals. Instead, the data is captured via other suitable signals, such as clock signals and CAS signals. [0017] RAM 34 includes a DLL structure 40 that receives differential clock signals CLK at 42 and bCLK at 44 and provides a locked output clock signal LCLK at 46. Differential clock signals CLK at 42 and bCLK at 44, also referred to as clock signal CLK at 42 and inverted clock signal bCLK at 44, provide a clock signal having a clock signal frequency that changes over a system frequency range, such as the frequency range of a dynamic frequency change environment. Differential clock signals CLK at 42 and bCLK at 44 are provided via any suitable clock circuit. In one embodiment, differential clock signals CLK at 42 and bCLK at 44 are provided via an external clock circuit controlled via controller 32 to provide clock signal frequencies over the frequency range. In one embodiment, differential clock signals CLK at 42 and bCLK at 44 are provided via controller 32 to provide clock signal frequencies over the frequency range. [0018] In other embodiments, DLL structure 40 receives a single ended clock signal, instead of differential clock signals CLK at 42 and bCLK at 44. Also, any of the clock signals herein, including locked clock signals such as locked output clock signal LCLK at 46, can be differential clock signals or single ended clock signals. [0019] DLL structure 40 provides locked output clock signal LCLK at 46, which is continuously locked to the frequency of differential clock signals CLK at 42 and bCLK at 44 over the system frequency range. DLL structure 40 provides locked output clock signal LCLK at 46 on a forward path of RAM 34 to be used internally and to provide data and strobe signals from RAM 34 to controller 32 via data communications path 38. The data and strobe signals are output signals having edges that correspond to or are aligned with edges in differential clock signals CLK at 42 and bCLK at 44. The edges of differential clock signals CLK at 42 and bCLK at 44 are delayed an integer number of clock cycles of the differential clock signals CLK at 42 and bCLK at 44 to provide edges in the data and strobe signals. In other embodiments, DLL structure 40 can be employed in any suitable integrated circuit to provide a continuously locked output clock signal in a dynamic frequency change environment or any suitable system environment. [0020] RAM 34 also includes an array of memory cells 50, a row address latch and decoder 52, a column address latch and decoder 54, a sense amplifier circuit 56, a RAM I/O circuit 58, an address register 60, and a control circuit 62. Conductive word lines 66, referred to as row select lines, extend in the x-direction across the array of memory cells 50. Conductive bit lines 68, referred to as digit lines, extend in the y-direction across the array of memory cells 50. A memory cell 70 is located at each cross point of a word line 66 and a bit line 68. Continue reading about Delay locked loop structure providing first and second locked clock signals... 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