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  Delay line, analog-to-digital converting device and load-sensing circuit using the sameUSPTO Application #: 20070247346Title: Delay line, analog-to-digital converting device and load-sensing circuit using the same Abstract: A delay line, an analog-to-digital converting device and a load-sensing circuit using the same are provided. The delay line comprises a delay-control terminal, a reset terminal, n delay cells DCELLx (0<x≦n). The delay cells DCELL1˜DCELLn are connected in series to each other. Each of the delay cells DCELLx is coupled to the delay-control terminal and the reset terminal for transmitting the first level stage by stage between the delay cells according to a delay time decided by the delay-control terminal in a sensing period. The outputs of all delay cells are reset to the second level when the sensing period is finished. The sensing period is decided by the signal from the reset terminal. Wherein, at least an Output tenninal ty (0<y≦n) of a delay cell DCELLy among the delay cells DCELL1˜DCELLn used as output terminal of the delay line. (end of abstract)
Agent: J C Patents, Inc. - Irvine, CA, US Inventors: Ke-Horng Chen, Li-Ren Huang, Hong-Wei Huang, Sy-Yen Kuo USPTO Applicaton #: 20070247346 - Class: 341155 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20070247346. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001]This application claims the priority benefit of Taiwan application serial no. 95114513, filed on Apr. 24, 2006. All disclosure of the Taiwan application is incorporated herein by reference. BACKGROUND OF THE INVENTION [0002]1. Field of Invention [0003]The present invention relates to a delay line. More particularly, the present invention relates to a delay line that transmits the first level stage by stage according to a delay time decided by the sensing period, and reset to the second level when the sensing period is finished, and an analog-to-digital converting device and a load-sensing circuit using the same. [0004]2. Description of Related Art [0005]Signal converting circuits are essential to electronic products that require data communication and image processing, even though we are now entering the system-on-chip (SOC) era. FIG. 1 is a circuit diagram of a common delay circuit. If a conventional delay circuit is applied to a signal converting circuit, as common delay circuits mainly adopt the voltage-control mode, that is, the input voltage V.sub.in to be converted into digital codes is taken as the supply voltage in the delay circuit, thus the delay difference in signal transmission will occur. However, as the voltage swing of the output signal of each of the delay cells is 0.about.V.sub.in, logic operation errors may occur at the back end decoder due to the difference between the voltage and the supply voltage of the decoder. In order to solve the problem, a level shifter is added to mediate and convert the voltage levels of the signals of the delay circuit and the decoder to be the same, such that the correct logic operation can be performed. If the error value of the trigger time of the delay signal to be processed is quite critical, the level shifter should be fast. Thus, the signal processing becomes complicated, and the power consumption increases as well. [0006]Furthermore, in order to improve the service lifetime of the product and the battery, the power consumption of the converting circuit and whether quick sensing and code conversion can be achieved become very important indices. FIG. 2 is a circuit diagram of a conventional signal converting circuit. A conventional signal converting circuit (e.g., an analog-to-digital converter) usually uses a large quantity of comparators CP and resistors R. A plurality of resistors R is connected in series to form a voltage divider, so as to further provide reference voltages at different levels to corresponding comparators CP. Each of the comparators compares the input voltage V.sub.in that is to be converted into digital codes and the corresponding reference voltage, and the comparators CP thus output digital codes corresponding to the input voltage V.sub.in. However, the number of comparators CP required will increase when the bit number of the digital codes to be generated is increased, thus aggravating the power consumption problem. SUMMARY OF THE INVENTION [0007]One objective of the present invention is to provide a delay line to transmit the first level stage by stage between delay cells according to the decided delay time in a sensing period, and reset the outputs of the delay cells to the second level when the sensing period is finished. [0008]Another objective of the present invention is to provide a load-sensing circuit to convert the load information related to the load into control signals so as to control the power supplier by using the time delay technology. [0009]Still another objective of the present invention is to provide an analog-to-digital converting device to convert the analog voltage into digital codes by using the time delay technology, such that low power consumption can be achieved, high precision irrelevant to temperature can be maintained, and thus the performance of the analog-to-digital converter is significantly improved. [0010]To achieve the aforementioned objectives, the present invention provides a delay line, which comprises a delay-control terminal, a reset terminal, and n delay cells DCELL.sub.x. DCELL.sub.x is the x.sup.th delay cell (0<x.ltoreq.n), and the delay cells DCELL.sub.1.about.DCELL.sub.n are connected in series to each other. Each of the delay cells DCELL.sub.x is coupled to the delay-control terminal and the reset terminal for transmitting the first level stage by stage between the delay cells according to a delay time decided by the delay-control terminal in a sensing period. The outputs of all delay cells are reset to the second level when the sensing period is finished. The sensing period is decided by the signal from the reset terminal. Wherein, at least an output terminal t.sub.y (0<y.ltoreq.n) of delay cell DCELL.sub.y among the delay cells DCELL.sub.1.about.DCELL.sub.n used as output terminal of the delay line. [0011]The present invention also provides a load-sensing circuit, which comprises a delay line, a sampling unit, and a voltage-current converter. The load-sensing circuit samples the load information in every sensing period, and converts the sampling result into control signals. The delay line comprises a delay-control terminal, a reset terminal, and n delay cells DCELL.sub.x. The delay cells DCELL.sub.1.about.DCELL.sub.n are connected in series. Each of the delay cells DCELL.sub.x is coupled to the delay-control terminal and the reset terminal for transmitting the first level stage by stage between the delay cells according to a delay time decided by the delay-control terminal in a sensing period. The output of each of the delay cells is reset to the second level when the sensing period is finished. The sensing period is decided by the signal from the reset terminal. Wherein, at least one output terminal t.sub.y (0<y.ltoreq.n) of delay cell DCELL.sub.y among the delay cells DCELL.sub.1.about.DCELL.sub.n for providing the control sinnal. The sampling unit samples. The sampling unit samples the load information when the sensing period starts. The voltage-current converter is coupled to the output of the sampling unit and the delay-control terminal of the delay line. The voltage-current converter converts the sampling result of the sampling unit and outputs the converted result, in which the converted result decides the delay time of the delay line. The output terminal t.sub.y of the delay line can serve as the control signal of the power supply device. [0012]The present invention further provides an analog-to-digital converting device, which comprises a delay line, a sampling unit, a voltage-current converter, and a latch unit. The analog-to-digital converting device samples the analog signals in every sensing period, and converts the sampling result into digital codes. The delay line comprises a control terminal, a reset terminal, and n delay cells DCELL.sub.x. The delay cells DCELL.sub.1.about.DCELL.sub.n are connected in series. Each of the delay cells DCELL.sub.x is coupled to the delay-control terminal and the reset terminal for transmitting the first level stage by stage between the delay cells according to a delay time decided by the delay-control terminal in a sensing period. The output of each of the delay cells is reset to the second level when the sensing period is finished. The sensing period is decided by the signal from the reset terminal. Wherein at least one output terminal t.sub.y of delay cell DCELL.sub.y among the delay cells DCELL.sub.1.about.DCELL.sub.n used as output terminal of the delay line. The sampling unit samples the analog signals when the sensing period starts. The voltage-current converter is coupled to the output of the sampling unit and the delay-control terminal of the delay line, so as to convert the sampling result of the sampling unit and output the converted result, in which the converted result decides the delay time of the delay line. The latch unit is coupled to the output terminal t.sub.y of delay cell DCELL.sub.y of the delay line, so as to latch the signal from the output terminal t.sub.y according to the trigger of the sampling pulse to output the digital codes. [0013]Compared with the conventional method that distinguishes the voltages by the comparators, the present invention uses the delay line to convert the electrical signal into the delay time, so as to obtain the corresponding digital codes. As no extra power is consumed after the inverter in the delay line finished signal transmission, compared with the continuous power consumption of the comparators, the delay line of the present invention has an advantage of low power consumption, and high precision irrelevant to temperature can be maintained, thereby significantly improving the performance of the analog-to-digital converter. [0014]In order to make the aforementioned and other objectives, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS [0015]FIG. 1 is a circuit diagram of a common delay circuit. [0016]FIG. 2 is a circuit diagram of a conventional signal converting circuit. [0017]FIG. 3 is a circuit diagram illustrating how the load-sensing circuit controls the power supply device according to the embodiment of the present invention. [0018]FIG. 4 is a circuit diagram illustrating the load-sensing circuit of FIG. 3 according to the embodiment of the present invention. [0019]FIG. 5 is a timing diagram of the relevant signals of FIGS. 3 and 4 according to the embodiment of the present invention. [0020]FIG. 6 is a detailed circuit diagram illustrating the voltage-current converter and the delay line of FIG. 4 according to the embodiment of the present invention. Continue reading... Full patent description for Delay line, analog-to-digital converting device and load-sensing circuit using the same Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Delay line, analog-to-digital converting device and load-sensing circuit using the same patent application. Patent Applications in related categories: 20080231489 - Analog-to-digital converter system with increased sampling frequency - The present invention is an improvement in sampling a high frequency input analog signal and converting it to a digital output signal. This is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. 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A set of output digital data produced from the A/D converter, following each A/D conversion, is acquired a plurality of times in succession within an interval that extends to the ... ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Delay line, analog-to-digital converting device and load-sensing circuit using the same or other areas of interest. ### Previous Patent Application: Digital-to-analog converter with secondary resistor string Next Patent Application: Electronic circuit device Industry Class: Coded data generation or conversion ### FreshPatents.com Support Thank you for viewing the Delay line, analog-to-digital converting device and load-sensing circuit using the same patent info. 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