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  Delay equalized z/2z ladder for digital to analog conversionDelay equalized z/2z ladder for digital to analog conversion description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060092065, Delay equalized z/2z ladder for digital to analog conversion. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application claims the benefit of U.S. Provisional Application Ser. No. 60/622,934, filed Oct. 29, 2004, titled, "Delay Equalized R-2R Ladder for High Speed, High Resolution Digital-to-Digital Conversion," which is incorporated herein by reference in its entirety. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The invention relates to digital to analog converters ("DACs") and to R/2R ladder networks. [0004] 2. Related Art [0005] Conventional DACs use what are known as R/2R ladder networks. Nodes within R/2R ladder networks have associated parasitic capacitances that cause propagation delays through the ladder networks. The propagation delays differ from node to node, which contributes non-linear artifacts in the output waveform. The non-linearities increase with increasing DAC conversion rates. [0006] What are needed therefore are ladder networks that do not have different propagation delays. SUMMARY OF THE INVENTION [0007] The present invention is directed to ladder networks with equalized propagation delays. A Z/2Z ladder network includes an R/2R ladder network having capacitors coupled across series resistors within the R/2R ladder network, wherein the capacitors are sized to substantially match delays from nodes within the ladder network to an output node. The Z/2Z ladder network can be implemented within a digital-to-analog converter ("DAC"), including higher resolution DACs, and high data rate DACs. In higher resolution DACs, and high data rate DACs, the Z/2Z ladder network is coupled through switches to corresponding current sources. The Z/2Z ladder is optionally implemented differentially. [0008] Additional features and advantages of the invention will be set forth in the description that follows. Yet further features and advantages will be apparent to a person skilled in the art based on the description set forth herein or may be learned by practice of the invention. The advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. [0009] It is to be understood that both the foregoing summary and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES [0010] The present invention will be described with reference to the accompanying drawings, wherein like reference numbers indicate identical or functionally similar elements. Also, the leftmost digit(s) of the reference numbers identify the drawings in which the associated elements are first introduced. [0011] FIG. 1 is a schematic diagram of an R/2R ladder network 100 with N bits. [0012] FIG. 2 is a schematic diagram of the R/2R ladder network 100, illustrating the Thevenin resistance of the R/2R ladder. [0013] FIG. 3 is a schematic diagram of an example DAC 300 including the R/2R ladder network 100. [0014] FIG. 4 is a schematic diagram of an example current-switched DAC 400, including the R/2R ladder network 100. [0015] FIG. 5 is a schematic diagram of the DAC 400, wherein parasitic capacitances are illustrated as capacitors Cp. [0016] FIG. 6 is a schematic diagram of a DAC 600, including a Z/2Z ladder network 602. [0017] FIG. 7 is a schematic diagram of a differential DAC 700. [0018] FIG. 8 is a schematic diagram of a differential switch within the differential DAC 700. DETAILED DESCRIPTION OF THE INVENTION I. Introduction Continue reading about Delay equalized z/2z ladder for digital to analog conversion... Full patent description for Delay equalized z/2z ladder for digital to analog conversion Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Delay equalized z/2z ladder for digital to analog conversion patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Delay equalized z/2z ladder for digital to analog conversion or other areas of interest. ### Previous Patent Application: Pwm driver and class d amplifier using same Next Patent Application: Delay equalized z/2z ladder for digital to analog conversion Industry Class: Coded data generation or conversion ### FreshPatents.com Support Thank you for viewing the Delay equalized z/2z ladder for digital to analog conversion patent info. IP-related news and info Results in 2.60435 seconds Other interesting Feshpatents.com categories: Daimler Chrysler , DirecTV , Exxonmobil Chemical Company , Goodyear , Intel , Kyocera Wireless , |
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