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Delay circuit and test apparatus

Delay circuit and test apparatus description/claims

This patent application claims priority from a Japanese Patent Application No. 2005-177851 filed on Jun. 17, 2005, the contents of which are incorporated herein by reference.

1. Field of the Invention

The present invention relates to a delay circuit that delays an input signal to output the signal and a test apparatus that tests a device under test. More particularly, the present invention relates to a delay circuit in which a plurality of delay elements is serially connected to one another.

2. Description of Related Art

Conventionally, a circuit that dulls a waveform of an input signal to delay the input signal by a predetermined delay amount has been known as a delay circuit for delaying the input signal. For example, there has been known a delay circuit that inputs an input signal into an inverter, charges and discharges load capacitance of the inverter, and outputs a voltage waveform in the load capacitance. The delay circuit adjusts rising time and falling time of the voltage waveform in the load capacitance and controls a delay amount to be given to the input signal by controlling a power source current of the inverter to control a charging and discharging current of the load capacitance.

However, when a conventional delay circuit has a large delay amount, a pulse from the delay circuit may become unsteady. For example, when the delay circuit charging and discharging the load capacitance has a large delay amount, a current value charging the load capacitance is reduced. The delay circuit charges the load capacitance for a period for which a pulse of the input signal shows an H-logic. However, since the charging current is small, the voltage of the load capacitance may not stand at a predetermined reference value or the time for which the voltage of the load capacitance stands at a value more than the reference value may not acquire sufficiently.

For such a problem, it is considered that a plurality of delay circuits is serially connected to one another and each delay circuit has a delay amount within a range in which a pulse is stable. However, in such a configuration, a waveform output from each delay circuit gets dull. Each delay circuit turns on/off its CMOS transistor according to the voltage of the input signal and charges and discharges the load capacitance by a power source current according to a delay setting. However, when the waveform of the signal received from the delay circuit in a previous stage gets dull, the timing in which the voltage enough to flow the power source current according to the delay setting is applied to the CMOS transistor gets late. Thus, the delay time in the delay circuit has an error with respect to the delay setting. Therefore, linearity for delay in the delay circuit has deteriorated.

Therefore, it is an object of the present invention to provide a delay circuit and a test apparatus that can solve the foregoing problems. The above and other objects can be achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.

To solve this problem, according to the first aspect of the present invention, there is provided a delay circuit that delays an input signal to output the delayed signal. The delay circuit includes: a first delay element operable to receive the input signal and delay the input signal to output the delayed signal; a buffer operable to receive the delay signal output from the first delay element and correct a dullness of a waveform of the delay signal generated from the first delay element to output the corrected signal; and a second delay element operable to receive the delay signal output from the buffer and delay the delay signal to output the delayed signal.

According to the second aspect of the present invention, there is provided a delay circuit that delays an input signal to output the delayed signal. The delay circuit includes: a first delay block operable to receive the input signal and delay the input signal to output the delayed signal; a second delay block operable to delay the delay signal output from the first delay block to output the delayed signal: and a second delay control block operable to control a delay amount of the second delay block, in which the first delay block and the second delay block respectively includes: a first delay element that receives the input signal and delays the input signal to output the delayed signal; a buffer that receives the delay signal output from the first delay element and corrects a dullness of a waveform of the delay signal generated from the first delay element to output the corrected signal; and a second delay element that receives the delay signal output from the buffer and delays the delay signal to output the delayed signal, the second delay control block includes: a flip-flop that divides a signal to be input into the first delay block to receive the divided signal and acquires a delay setting data to control the delay amount according to the signal to be input into the first delay block; and a delay controlling unit that controls the delay amount of the second delay block based on the delay setting data acquired by the flip-flop.

According to the third aspect of the present invention, there is provided a test apparatus that tests a device under test. The test apparatus includes: a pattern generator operable to generate a test pattern testing the device under test; a waveform shaper operable to shape a test signal to be supplied to the device under test based on the test pattern and supply the shaped signal to the device under test; and a timing generator operable to generate a timing signal controlling the timing in which the waveform shaper supplies the test signal to the device under test, in which the timing generator includes: a first delay element that receives a reference signal and delays the reference signal to output the delayed signal; a buffer that receives the delay signal output from the first delay element and corrects a dullness of a waveform of the delay signal generated from the first delay element to output the corrected signal; and a second delay element that receives the delay signal output from the buffer and delays the delay signal to output the timing signal.

The summary of the invention does not necessarily describe all necessary features of the present invention. The present invention may also be a sub-combination of the features described above.

FIG. 1 is a view exemplary showing a configuration of a delay circuit according to an embodiment of the present invention.

FIG. 2A shows waveforms of an input signal and a delay signal in a conventional delay circuit, and FIG. 2B shows a waveform in a first delay element.

FIG. 3A is a view exemplary showing a current waveform charging load capacitance in a second delay element, and FIG. 3B is a view exemplary showing a voltage waveform of the load capacitance.

FIG. 4 is a view exemplary showing a configuration of a delay circuit according to an embodiment of the present invention.

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