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  Delay cell of voltage controlled delay line using digital and analog control schemeUSPTO Application #: 20070069780Title: Delay cell of voltage controlled delay line using digital and analog control scheme Abstract: Provided is an analog/digital control delay locked loop (DLL). The DLL includes a phase detector for detecting a phase difference between an input clock signal and a feedback signal to provide an up detection signal or a down detection signal, a charge pump for generating an adjusted output current based on the up or down signals, a loop filter for low pass-filtering the output current to produce an analog control voltage, a voltage controlled delay Line (VCDL) for receiving the analog control voltage, the input clock signal and a digital code, and delaying the input clock signal based on the analog control voltage and the digital code to provide an output clock signal, a delay replica modeling unit formed by replica of delay factors for producing the feedback signal depending on the output clock signal, and a digital code generator for generating the digital code. (end of abstract)
Agent: Blakely Sokoloff Taylor & Zafman - Los Angeles, CA, US Inventor: Yong-Ju Kim USPTO Applicaton #: 20070069780 - Class: 327158000 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20070069780. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates to semiconductor design technologies; and, more particularly, to a delay locked loop (DLL) for use in a synchronous dynamic random access memory (SDRAM), which is capable of determining a coarse delay amount by increasing an operating range of a delay cell. DESCRIPTION OF RELATED ART [0002] In memory designs, time taken for passing through a clock buffer inside a chip, among clock skew factors obstructing high-speed data transmission is important to determine major timing parameters of DRAM. An external clock should be accepted through the clock buffer because it is not inputted at CMOS level and also be passed through a clock driver circuit with large driving capacity for supplying an internal clock signal to many internal circuits. Therefore, the internal clock signal has a delay compared to the external clock; and various internal circuits always have a constant delay with respect to the external clock by a control of the internal clock. Thus, a clock access time tAC, which denotes time taken from receipt of the external clock to output of data, is increased by the delay component, thus causing a burden for designing a system. For the above reason, a high speed operation of DRAM is impossible. Circuits that achieve a high speed operation of memory by removing the delay components, include a phase locked loop (PLL) circuit and a DLL circuit. [0003] Basically, the DLL includes a phase comparator for periodically comparing a phase of an external clock signal with that of an internal clock signal and detecting whether to increase or decrease the phase depending on a phase difference therebetween, a charge pump for generating a constant output voltage level based on a phase increase/decrease signal, and a loop filter for filtering a high frequency component of the output voltage level from the charge pump, like the PLL circuit. In receiving the output voltage level from the loop filter, the PLL using a voltage controlled oscillator (VCO) is distinguished from the DLL using a voltage controlled delay line (VCDL). [0004] On the other hand, locking is very important in high speed memory. In particular, a delay tracking range of DLL is very important in a memory with a wide range of operating frequencies. Namely, because a range of control voltage becomes small in the DLL as an operating voltage is lower, it is very difficult to manufacture a chip with an operating range from hundreds of MHz to dozens of GHz. [0005] FIG. 1 is a block diagram for describing a basic operation of a conventional analog control DLL. [0006] Referring to FIG. 1, the conventional analog control DLL includes a phase detector 10 for receiving an input clock signal FREF and a feedback signal FEEDBACK_CLK, which is provided by modeling an output clock signal FOUT in delay factors inside a memory, and detecting a phase difference between the two signals to produce an up detection signal UP or a down detection signal DOWN, a charge pump 20 for taking the up or down detection signals UP or DOWN from the phase detector 10, and increasing an output current IC in response to the up detection signal UP and decreasing it in response to the down detection signal DOWN, a loop filter 30 for low pass-filtering the increased/decreased output current IC to generate an analog control voltage VCTRL, a voltage controlled delay line (VCDL) 40 for receiving the analog control voltage VCTRL and the input clock signal FREF and delaying the input clock signal FREF by a certain value corresponding to the analog control voltage VCTRL to provide a delayed signal as the output clock signal FOUT, and a delay replica modeling unit 50 for accepting and modeling the output clock signal FOUT in delay factors to produce the feedback signal FEEDBACK_CLK. [0007] FIG. 2 is a block diagram for describing a configuration of the general VCDL 40 shown in FIG. 1. [0008] The VCDL 40 may be implemented with a plurality of delay cells, 40A to 40D, which delays input clock signals IN and INB by a preset delay value and provides delayed signals as output clock signals OUTB and OUT. The input clock signals IN and INB are differential signals of the input clock signal FREF. The output clock signals OUTB and OUT output from the last delay cell 40D are differential signals of the output clock signal FOUT. [0009] FIG. 3 shows a detailed circuit diagram of one of the plurality of delay cells of FIG. 2. [0010] Referring to FIG. 3, each delay cell includes NMOS transistors 44 and 45 whose gates take the input clock signals IN and INB and sources are coupled to each other, a pair of symmetrical loads 42 and 43 connected between a power supply voltage VDD and each of the NMOS transistors 44 and 45, and an NMOS transistor 46 connected between the sources of the NMOS transistors 44 and 45 and ground voltage VSS. Each of the symmetrical loads 42 and 43 has a same structure, wherein each load may be composed of two PMOS transistors connected in parallel, one having a structure that its drain and gate are coupled and the other receiving an analog control voltage PCTRL via the gate to control a delay value. [0011] In operation, inputted to the gates of the NMOS transistors 44 and 45 are the input clock signals IN and INB, which are delayed by a preset value depending on the analog control voltage PCTRL inputted to the symmetrical loads 42 and 43 to provide delayed signals as the output signals OUTB and OUT. Meanwhile, the NMOS transistor 46 connected to the VSS can compensate a variation of drain and substrate voltages in response to an analog control voltage NCTRL. The analog control voltages PCTRL and NCTRL are differential signals of the analog control voltage VCTRL shown in FIG. 1. [0012] FIG. 4 depicts a graph for describing characteristics of the nonlinear analog control voltage VCTRL of the delay cell of FIG. 3. [0013] Referring to FIG. 4, a horizontal axis of the graph shows the analog control voltage VCTRL and a vertical axis thereof denotes a delay time per delay cell. It can be seen that the delay time according to the analog control voltage VCTRL is varied depending on the process variation of the plurality of delay cells of FIG. 3. For example, the linear analog control voltage VCTRL approximately ranges from 0.7 V to 1 V at operation voltage of 1.5 V. Within this operating range, a typical case has a delay range from 60 ps to 32 ps, a slow case has a delay range from 99 ps to 44 ps, and a fast case has a delay range from 40 ps to 23 ps. In this case, speed binning of product should be used according to the process. Furthermore, in the slow case, a large variation of delay is caused, in spite of a small variation of control voltage VCTRL by noise. Accordingly, the DLL circuit is very sensitive to noise when it operates in a wide frequency range. Conversely, in the fast case, a stable delay can be guaranteed in operating in a wide frequency range, but a wide range of delay operations cannot be performed. SUMMARY OF THE INVENTION [0014] It is, therefore, an object of the present invention to provide a delay cell circuit of VCDL using a digital and analog control scheme for maximizing its operating range through a combination of a digital control and an analog control. [0015] In accordance with an aspect of the present invention, there is provided an analog/digital control DLL including: a phase detector for receiving an input clock signal and a feedback signal and detecting a phase difference between the two signals to provide an up detection signal or a down detection signal; a charge pump for taking the up detection signal or the down detection signal and generating an adjusted output current based on the signals; a loop filter for low pass-filtering the output current to produce an analog control voltage; a VCDL for receiving the analog control voltage, the input clock signal and a digital code, and delaying the input clock signal based on the analog control voltage and the digital code to generate an output clock signal; a delay replica modeling unit formed by replicas of a delay factor for receiving the output clock signal and producing the feedback signal; and a digital code generator for generating the digital code. [0016] Preferably, the VCDL includes a plurality of delay cells connected in series, and each delay cell includes: a differential input transistor unit for receiving differential input clock signals; an analog control transistor unit whose one terminal is connected to a power supply terminal for adjusting a fine delay amount in response to analog control voltages; and a digital control transistor unit connected between the analog control transistor unit and the differential input transistor unit for adjusting a coarse delay amount in response to a digital code. In addition, the delay cell of the VCDL further includes first and second output nodes connected to each drain of transistors included in the differential input transistor unit for generating differential output clock signals, respectively. [0017] Preferably, the analog control transistor unit includes: an analog control load transistor circuit whose one terminal is connected to the power supply terminal, driven in response to a first analog control voltage; and an analog control current source transistor circuit whose one terminal is connected to a ground voltage terminal, driven in response to a second analog control voltage. The digital control transistor unit includes: a digital control load transistor circuit connected between the other terminal of the analog control load transistor circuit and the first and second output nodes, driven in response to the digital code; and a digital control current source transistor circuit connected between the common source of the differential input transistor unit and the analog control current source transistor circuit, driven in response to a complementary value of the digital code. BRIEF DESCRIPTION OF THE DRAWINGS [0018] The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which: [0019] FIG. 1 is a block diagram for describing a basic operation of a conventional analog control DLL; [0020] FIG. 2 is a block diagram for describing a configuration of the general voltage controlled delay line (VCDL) 40 shown in FIG. 1; Continue reading... Full patent description for Delay cell of voltage controlled delay line using digital and analog control scheme Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Delay cell of voltage controlled delay line using digital and analog control scheme patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. 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