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  De-coupling capacitors produced by utilizing dummy conductive structures integrated circuitsUSPTO Application #: 20070108554Title: De-coupling capacitors produced by utilizing dummy conductive structures integrated circuits Abstract: A de-coupling capacitor module using dummy conductive elements in an integrated circuit is disclosed. The de-coupling module comprises at least one circuit module having one or more active nodes, and at least one dummy conductive element unconnected to any active node, and separated from a high voltage conductor or a low voltage conductor by an insulation region to provide a de-coupling capacitance. (end of abstract) Agent: Duane Morris, LLPIPDepartment - Philadelphia, PA, US Inventors: Cliff Hou, Lee-Chung Lu, Chia-Lin Cheng USPTO Applicaton #: 20070108554 - Class: 257532000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Integrated Circuit Structure With Electrically Isolated Components, Passive Components In Ics, Including Capacitor Component The Patent Description & Claims data below is from USPTO Patent Application 20070108554. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATION [0001] This application is a divisional of U.S. patent application Ser. No. 10/952,259 filed Sep. 27, 2004, the contents of which are hereby incorporated by reference, as if set forth in their entirety. BACKGROUND [0002] The present invention relates generally to integrated circuits (IC), and more particularly to the reduction of IC power noise generation through the utilization of dummy conductor configurations to increase the de-coupling capacitance within the IC. [0003] Capacitors are a class of passive electronic elements useful for reduction of unwanted noise, for coupling of AC signals, and for constructing timing and phase shift networks. They are relatively bulky devices that store energy in electrostatic fields. The microscopic dimensions of today's ICs preclude the fabrication of more than a few hundred pico-farads of capacitance in an IC. Since conventional IC capacitor construction techniques limit an IC to a few hundred pico-farads, larger capacitors must reside off-chip (located on the associated printed circuit board). These off-chip capacitors are bulky and require significant PCB board space as well as additional material and processing costs. Also, due to their increased distance from the noise generating point within the IC, these off-chip capacitors are not as effective in IC noise reduction as the internal capacitors. [0004] All of the capacitors used in ICs are of the sort called "parallel plate" capacitors, which consist of two conductive plates called "electrodes" attached to either side of a slab of insulating material typically known as dielectric. In the simple parallel-plate capacitor, the two electrodes are assumed to have the same dimensions and to reside directly opposite from one another. The value of the simple parallel-plate capacitor can be computed using the following approximate equation: C=0.0885A(e.sub.r)/t where C is the capacitance in pico-farads, A is the area of either electrode in square microns (um.sup.2), t is the thickness of the dielectric in Angstroms, and e.sub.r is a dimensionless constant called the "relative permittivity." [0005] e.sub.r depends upon the nature of the dielectric and is sometimes called the "dielectric constant." Consider a capacitor with a plate area of 0.1 mm.sup.2 constructed using a 200 A dry oxide film. If the dielectric permittivity is 4, then the capacitance will be approximately 180 pico-farads. This example explains why it is difficult to obtain internal capacitors of more than a few hundred pico-farads. As the IC geometries delve into the sub-micron level, internal IC capacitance will continue to decrease. Reducing the thickness of the dielectric increases the capacitance, but also increases the electric field across the dielectric. If the electric field increases beyond a certain point, a catastrophic short circuit of the capacitor is possible. [0006] Current ICs have two typical capacitor types, either MOS capacitors or poly-poly capacitors. MOS capacitors consist of a thin layer of grown oxide formed on a silicon diffusion that serves as one of the electrodes. The other electrode consists of either metal or doped polysilicon. If the gate oxide is used to form a MOS capacitor, the resulting structure is called a "gate oxide capacitor". [0007] MOS capacitors have a number of disadvantages. These MOS capacitors are designed into the IC to provide as much de-coupling capacitance as possible to minimize IC internal noise generation. It utilizes unused areas within the IC. However, these devices require a large amount of chip area (typically 10-15% of chip area) that could have been used for additional circuitry or for a higher density of IC devices per wafer. Also, MOS devices have an inherently large device leakage current through the thinner gate oxide, especially for 90-nanometer and smaller IC geometries. This leakage current causes excessive power dissipation within the IC in both static and dynamic states. Also, because of the thin gate oxide layer in MOS devices, these devices are more susceptible to electro-static discharge (ESD) anomalies. [0008] Poly-poly capacitors employ two polysilicon electrodes in combination with either an oxide or oxide-nitride-oxide (ONO) dielectric. Many CMOS and Bi-CMOS processes already incorporate multiple polysilicon layers, so poly-poly capacitors do not necessarily require any additional masking steps. Poly-poly capacitors normally reside over field oxide. Oxide steps should not intersect the structure because they can cause surface irregularities in the lower capacitor electrode. [0009] Both the MOS capacitor and the poly-poly capacitor structures are considered thin-film capacitors. The microscopic dimensions of today's integrated circuits preclude the fabrication of more than a few hundred pico-farads of capacitance in an IC using either the MOS or poly-ploy capacitors. [0010] Desirable in the art of IC design are additional circuits to reduce IC power system internal power noise generation by increasing the internal IC de-coupling capacitance between the IC power and ground. SUMMARY [0011] In view of the foregoing, this invention provides a de-coupling capacitor module using dummy conductive elements in an integrated circuit and the method for forming the same. The de-coupling module comprises at least one circuit module having one or more active nodes, and at least one dummy conductive element unconnected to any active node, and separated from a high voltage conductor or a low voltage conductor by an insulation region to provide a de-coupling capacitance. [0012] Although the invention is illustrated and described herein as embodied in circuits and methods to reduce IC power noise generation through the incorporation of additional internal IC de-coupling capacitance, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. BRIEF DESCRIPTION OF THE DRAWINGS [0013] FIG. 1 presents a conventional IC interleaved metal layer structure. [0014] FIG. 2 illustrates a dummy conductor structure that adds additional IC de-coupling capacitance in accordance with one embodiment of the present invention. [0015] FIG. 3 illustrates a dummy conductor structure that adds additional IC de-coupling capacitance in accordance with another embodiment of the present invention. DESCRIPTION [0016] The present invention provides a de-coupling system to reduce IC internal power noise generation and static/dynamic IR-drop. The de-coupling system adds internal IC de-coupling capacitance between a high voltage conductor, such as a power line, and a low voltage conductor, such as a grounded line. The de-coupling system can be implemented by utilization of "line style" and "square style" dummy conductive elements in the same or different layers within the IC. The incorporation of these two styles can be easily identifiable from the IC layout. [0017] FIG. 1 presents a conventional IC interleaved metal layer structure 100. A box 102 shows a lateral view of an IC with six metal layers (M1-M6) and an IC substrate layer. The first metal layer M1 is a ground layer and is tied directly to the IC substrate by a contact 104. Both the substrate layer and the M1 layer are tied to ground, as represented by the label GND. In a typical interleaved layer structure, each subsequent vertical metal layer (M1 through M6) alternates between ground or VCC (as shown in the box 102) to take advantage of a plurality of intrinsic capacitances 106 generated between the various metal layers. The GND layers (M1, M3 and M5) are tied to IC GND, while the VCC layers (M2, M4 and M6) are tied to VCC via connections between layers. The intrinsic capacitances 106 in effect act as a system of parallel de-coupling capacitances and are useful for internal power noise reduction. The intrinsic capacitances 106 add to the MOS and poly-poly capacitance that is already designed into the IC for de-coupling. The total capacitance, or the aggregate capacitance of the intrinsic capacitances 106, varies, however, by the extent of the metal on each layer as well as by the physical distance between the layers. [0018] FIG. 2 illustrates the new "line style" dummy conductive element that adds additional de-coupling capacitance to an IC in accordance with one embodiment of the present invention. The drawing 200 represents a section of an IC utilizing the "line style" dummy conductive elements for additional de-coupling capacitance. Capacitance formed in this configuration is called "Metal on Metal" (MoM) capacitance. Box 202 shows the boundaries of this section of the IC with its various circuit modules 204, a high voltage conductor 206, such as a power line, a low voltage conductor 208, such as a grounded line, and dummy conductor elements 210 and 212, such as metal lines and doped polysilicon lines. The high voltage conductor 206, low voltage conductor 208, and the components within the circuit modules 204 are connected to at least one active node that interconnects them for a normal operation. [0019] The dummy conductive elements 210 and 212 are connected to a voltage different from its neighboring high voltage conductor 206 or the low voltage conductor 208, and are separated therefrom by an insulation region. For example, the de-coupling capacitance is formed by running the grounded dummy conductive elements 210 adjacent to the high voltage conductor 206, such as a Vcc power line, or running VCC connected dummy conductive elements 212 adjacent to the low voltage conductor 208, such as a ground line. These dummy conductive elements 210 and 212 are not connected to any active node within the IC circuit other than its connection to ground or VCC for the creation of the de-coupling capacitance, and they are appropriately named "dummy conductive element." For the purpose of this invention, the term "active node" refers to nodes in an active circuit module that are not connected to any power supply. These dummy conductive elements can be routed throughout the layer next to VCC or GND lines wherever an unused area exists. It can also be routed around circuit modules 204 if required. The de-coupling capacitance 214 is formed by the parallel routing of the dummy conductive elements 210 close to the high voltage conductor 206. The maximum de-coupling capacitance 214 is created by routing the maximum parallel length between these lines. The de-coupling capacitance 216 is also formed by the parallel routing of the VCC connected dummy conductive elements 212 close to the low voltage conductors 208. As before, the maximum de-coupling capacitance 216 is created by routing the maximum parallel routing length between these lines. Additional de-coupling capacitance 218 may be formed where the grounded dummy conductive elements 210 parallel other VCC connected dummy conductive elements 212. The goal of adding de-coupling capacitance for IC power noise reduction is to create the maximum de-coupling capacitance possible rather than a specific capacitance value. The capacitance generated can be optimized by the selection of the proper line width, spacing between lines, and length of the parallel routing. Continue reading... Full patent description for De-coupling capacitors produced by utilizing dummy conductive structures integrated circuits Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this De-coupling capacitors produced by utilizing dummy conductive structures integrated circuits patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. 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