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05/08/08 - USPTO Class 710 |  7 views | #20080109576 | Prev - Next | About this Page  710 rss/xml feed  monitor keywords

Data transfer apparatus, storage device control apparatus and control method using storage device control apparatus

USPTO Application #: 20080109576
Title: Data transfer apparatus, storage device control apparatus and control method using storage device control apparatus
Abstract: A data transfer apparatus includes a memory having first and second queues for storing data transfer information that includes information specifying a first memory area and information specifying a second memory area, a first processor which registers the data transfer information in the first or second queue, and a second processor performing a processing to transfer data stored in the first memory area to the second memory area. The second processor reads out the data transfer information registered in the first queue, transfers the data based on the read data transfer information, and decides if data transfer information succeeding to the read data transfer information is registered in the first queue. If the succeeding data transfer information is registered, the second processor reads out the succeeding data transfer information from the first queue, and performs the data transfer processing based on the read data transfer information.
(end of abstract)
Agent: Townsend And Townsend And Crew, LLP - San Francisco, CA, US
Inventors: Masayuki FURUKAWA, Takahiko TAKEDA
USPTO Applicaton #: 20080109576 - Class: 710039000 (USPTO)

Related Patent Categories: Electrical Computers And Digital Data Processing Systems: Input/output, Input/output Data Processing, Input/output Access Regulation, Access Request Queuing
The Patent Description & Claims data below is from USPTO Patent Application 20080109576.
Brief Patent Description - Full Patent Description - Patent Application Claims  monitor keywords

[0001] The present application claims priority from Japanese application JP2003-400512 filed on Nov. 28, 2003, the content of which is hereby incorporated by reference into this application.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to data transfer apparatus, storage device control apparatus and control method using the storage device control apparatus.

[0003] Data has so far been transferred directly between memory and device not through CPU by the widely used DMA transfer technique using a DMA (Direct Memory Access) controller. When the DMA transfer occurs, the CPU gives the DMA controller the information necessary for the data transfer such as the transfer source and destination so that the information can be set in the controller, and commands it to make the data transfer processing. The DMA controller, when instructed to do the data transfer processing, transfers data not through the CPU. For example, refer to JP-A-2003-91497.

SUMMARY OF THE INVENTION

[0004] In the conventional DMA transfer processing, however, since the CPU directly sets the information such as data source and destination in the register of the DMA controller, it takes a considerable amount of time for the CPU to set this information in the DMA controller particularly when the data transfer processing is made at frequent intervals. In addition, when the DMA controller finishes the data transfer processing, it informs the CPU of this fact by a process like interruption. However, as the data transfer processing is frequently made, this notice from the DMA controller to the CPU happens quite often, thus frequently interrupting the CPU's operation.

[0005] In view of this background, the invention is to provide a data transfer control method, data transfer apparatus, storage device control apparatus, control method using the storage device control apparatus, and channel adapter that all can make efficient use of the CPU.

[0006] According to this invention, there is provided a data transfer apparatus that includes a memory having first and second queues for storing data transfer information that includes information for specifying a first memory area and information for specifying a second memory area, a first processor for causing the data transfer information to be registered in the first or second queue, and a second processor for making data transfer processing to transfer data stored in the first memory area to the second memory area, wherein the second processor reads out the data transfer information registered in the first queue, makes the data transfer processing on the basis of the read data transfer information, and decides if the data transfer information that follows the read data transfer information is registered in the first queue, in which case, if the succeeding data transfer information is registered in the first queue, the second processor reads out the succeeding data transfer information from the first queue, and makes the data transfer processing on the basis of the read data transfer information, while if the succeeding data transfer information is not registered in the first queue, the second processor reads out the data transfer information from the second queue, and makes the data transfer processing on the basis of the read data transfer information.

[0007] The invention provides a data transfer apparatus, a storage device control apparatus and a control method using the storage device control apparatus that all can make efficient use of the CPU.

[0008] Other objects, features and advantages of the invention will become apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1 is a block diagram showing a computer according to the first embodiment of the invention.

[0010] FIG. 2 is a diagram showing one example of data transfer information according to the first embodiment of the invention.

[0011] FIG. 3 is a flowchart showing the flow of data transfer processing according to the first embodiment of the invention.

[0012] FIG. 4 is a flowchart showing the flow of processes for DMA controller 60 to stop the data transfer processing according to the first embodiment of the invention.

[0013] FIG. 5 is a block diagram showing the whole arrangement of an information processing system as the second embodiment of the invention.

[0014] FIG. 6 is a block diagram showing the hardware construction of channel control unit 210 according to the second embodiment of the invention.

[0015] FIG. 7 is a block diagram showing the construction of data transfer LSI 500 according to the second embodiment of the invention.

[0016] FIG. 8 is a table showing the details of data transfer information that the data transfer LSI 500 needs for data transfer according to the second embodiment of the invention.

[0017] FIG. 9 is a table showing one example of end status information that the data transfer LSI 500 writes in local memory 212 when the data transfer LSI 500 finishes data transfer according to the second embodiment of the invention.

[0018] FIG. 10 is a table showing the registers that the data transfer LSI 500 has according to the second embodiment of the invention.

[0019] FIG. 11 is a flowchart showing the flow of the data transfer processing using a transfer information list according to the second embodiment of the invention.

DESCRIPTION OF THE EMBODIMENTS

[0020] Embodiments of the invention will be described in detail with reference to the accompanying drawings.

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