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  Data retention in operational and sleep modesThe Patent Description & Claims data below is from USPTO Patent Application 20070085585. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] This invention relates to the field of data processing systems. More particularly, this invention relates to circuits and methods of operating circuits that allow for the storage of a signal value in both operational and sleep modes. [0003] 2. Description of the Prior Art [0004] In many circuits, particularly those that run off remote power supplies such as batteries, it is important to keep the power consumption of the circuits low. As well as addressing the issue of operational circuit efficiency attention is also being turned to reducing static power consumption, i.e. power loss due to leakage currents. One way of addressing this is to provide the circuit with a sleep mode so that it is in effect powered down during these non-operational periods. To reduce static power during these sleep periods, many circuit designs are now making use of on-chip power gating which allows rapid transitions between sleep and functional modes. This power gating is achieved by inserting power transistors between the targeted circuitry and Vdd creating a "virtual" Vdd rail, or by inserting power transistors between the targeted circuitry and Vss creating a "virtual" Vss rail. To enter a low leakage mode, the power transistors are turned off and the leakage of the design is limited by the leakage of the power transistors. Since the power transistors can be made to be high Vt (threshold voltage), and since the width of the power transistors can be much less than the width of the active devices in the circuit, leakage currents can be dramatically reduced. Thus, when the power transistors are turned off the virtual power rail at their output floats and the circuit is powered down. [0005] Although this results in substantial power savings it also results in a loss of state within the targeted circuitry. If it is desired that the circuit retain state during sleep mode, data retention circuits such as special data retention flip-flops must be used within the design. Such a mode of operation allows the stored signal values to be securely held in a small portion of the circuitry whilst the remainder of the circuitry is powered down for leakage reduction purposes. When power is resumed, the saved signal value is restored and operation continues. [0006] A common prior art approach to data retention is to provide an additional third storage or balloon latch that is not in the data pathway of the other two latches of a flip flop and to store data in this third latch during sleep mode. This latch has its own power supply and can be built of high threshold components. Such a system is described in "A 1-V High Speed MTCMOS Circuit Scheme for Power-Down Application Circuits" IEEE Journal of Solid-State Circuits, Vol 32, No 6, June 1997. A disadvantage of this approach is that the balloon latches consume considerable additional circuit area. [0007] It has also been proposed for sense amplifier flip-flops and hybrid latch flip-flops which have associated scan cells that operate in accordance with the level sensitive scan design methodology to reuse the scan cells for data retention during a power down mode of operation. Whilst this approach reduces the increase in circuit overhead associated with providing the data retention capability, it does require control of the three clock signals of the sense amplifier flip-flops or hybrid latch flip-flops with their known disadvantages in terms of speed, power consumption and other factors. It is also only applicable to flip flops having dedicated scan latches. [0008] "Lower Power Integrated Scan-Retention Mechanism" ISPLED August 2002, also addresses this problem. [0009] Co pending U.S. application Ser. No. 11/088268 having the same assignee as this patent also addresses this problem. SUMMARY OF THE INVENTION [0010] A first aspect of the present invention provides a circuit for retaining a signal value during a sleep mode while a portion of said circuit is powered down comprising: a clock signal input operable to receive a clock signal; at least one latch clocked by said clock signal; a data input, a data output and a forward data path therebetween, wherein a signal value is operable to be received at said data input, is clocked into said at least one latch and passes to said data output along said forward data path; wherein at least one of said at least one latch comprises a retention latch operable to retain a signal value during said sleep mode; and said circuit further comprises a bidirectional tristateable device, said bidirectional tristateable device being arranged between said forward data path and said retention latch and being operable to selectively isolate said retention latch from said forward data path in response to receipt of a first sleep signal; wherein in response to receipt of a second sleep signal, said second sleep signal being received after said first sleep signal, said circuit is operable to enter said sleep mode such that a voltage difference across said portion of said circuit is reduced such that said portion of said circuit is powered down, and a voltage difference across said retention latch and said bidirectional tristateable device is maintained. [0011] The arrangement of the present invention that provides a data retention device that can retain data in sleep mode and is not itself on the forward data path, is an effective way of retaining data without slowing the critical timing path, which comprises the forward data path. Furthermore, the use of a tristateable device placed between the forward data path and the retention latch which can selectively isolate the retention latch, is a convenient way of retaining data in sleep mode and again does not effect the critical timing path. Removing these devices from the critical timing path allows the designer greater freedom in his selection of components for these devices and therefore allows for the selection of, for example, low leakage components that may not have such high performance. [0012] Although it is possible for there to be only one latch, in most embodiments the circuit comprises a plurality of latches clocked by said clock signal, said signal value passing from one of said plurality of latches to a subsequent one of said plurality of latches along said forward data path, at least one of said plurality of latches comprising said retention latch. [0013] In some embodiments, said bidirectional tristateable device comprises two transistors operable to receive said first sleep signal and arranged such that in response to receipt of said first sleep signal said two transistors form a high impedance path and in response to not receiving said first sleep signal said two transistors form a low impedance path. [0014] In other embodiments, said bidirectional tristateable device comprises four transistors, two of said four transistors forming said bidirectional tristateable device and two of said four transistors forming an inverter operable to invert said first sleep signal prior to inputting it to one of said two transistors. [0015] Depending on whether an inverted sleep signal is available within the circuit, the bidirectional tristateable device may be provided by two or four transistors. In either case the provision of just a few transistors is sufficient to adapt a traditional latch into a retention latch in some embodiments. Thus, a retention latch is achieved with a small increase in circuit area. [0016] Although any sort of bidirectional tristateable device may be used, in some embodiments the bidirectional tristateable device comprises a transmission gate. Any tristateable devices that provide a low impedance in response to one input and a high impedance in response to another would be appropriate, but a transmission gate is found to be particularly effective. [0017] In some embodiments, said data retention latch does not receive said clock signal while in others said data retention latch is operable to receive said clock signal. [0018] Although it is possible to provide a latch circuit that is not clocked, it is found that one that is clocked can switch between states more easily and thus, may be preferred in some embodiments. [0019] In some embodiments, said circuit further comprises clock signal distribution means operable to distribute said clock signal to said retention latch. [0020] Although the clock signal may be generated outside of the circuit in others it is generated within the circuit. Distributing the clock to the retention latch enables a clocked retention latch to switch state. [0021] Although provision of the clocked signal to the retention latch enables it to switch state more easily, it does have a drawback in that power needs to be supplied to the clock distribution in sleep mode and this can add significantly to static power loss. [0022] In some embodiments, said clock signal distribution means comprises a first sleep signal input operable to receive a first sleep signal; wherein in response to said first sleep signal said clock signal distribution means is operable to hold said clock signal at a predetermined value such that said retention latch retains state. Continue reading... Full patent description for Data retention in operational and sleep modes Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Data retention in operational and sleep modes patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Data retention in operational and sleep modes or other areas of interest. ### Previous Patent Application: Data latch circuit and electronic device Next Patent Application: Clock control circuit for reducing consumption current in data input and output operations and semiconductor memory device including the same and data input and output operations methods of semiconductor memory device Industry Class: Miscellaneous active electrical nonlinear devices, circuits, and systems ### FreshPatents.com Support Thank you for viewing the Data retention in operational and sleep modes patent info. IP-related news and info Results in 0.26637 seconds Other interesting Feshpatents.com categories: Tyco , Unilever , Warner-lambert , 3m |
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