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Data restoration in case of page-programming failureData restoration in case of page-programming failure description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070086244, Data restoration in case of page-programming failure. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This patent application claims the benefit of U.S. Provisional Patent Application No. 60/726,819 filed Oct. 17, 2005. FIELD AND BACKGROUND OF THE INVENTION [0002] The present invention relates to systems and methods for restoring data in flash memory after an operational failure. Writing and erasing data in flash memories is well-known in the art. [0003] The operation of flash memories is described in Ronen, US Patent Publication No. 20050243626 (assigned to the assignee of the present invention and henceforth referred to as Ronen '626), which patent application is incorporated by reference for all purposes as if fully set forth herein. FIG. 1 (adapted from FIG. 1 of Ronen '626) shows the storage of a bit, either a zero-bit or a one-bit, in a cell of an electrically programmable memory (EPROM) such as a flash memory. A cell is a memory element containing values of one or more data bits. For historical reasons, this process of storing (or writing) data in an EPROM is called "programming" the EPROM. The terms "writing" and "programming" are used interchangeably herein. Specifically, the cell, that is the subject of FIG. 1, stores one bit of data, and so commonly is called a single-level cell (SLC). Initially, the cell has a nominal threshold voltage V.sub.1 that represents a one-bit. For example, after a block of a flash memory has been erased, all the cells have nominal threshold voltages V.sub.1. [0004] Because of unavoidable inaccuracies in the initializations of the cells, the actual threshold voltages are distributed around the nominal threshold voltage V.sub.1 according to a distribution curve 10. Then, to each cell that is to store a zero-bit, a train of programming voltage pulses is applied, in order to inject electrons from the cell's silicon substrate through the cell's oxide layer into the cell's floating gate, until the cell's threshold voltage exceeds a reference voltage V.sub.0 that represents a zero-bit. Because the electrons move through the oxide layer by quantum mechanical tunneling or by hot injection, because of non-uniformities in the cells' structures, and because the initial threshold voltages are distributed according to distribution curve 10, the threshold voltages of the cells that store zero-bits are distributed above V.sub.0 according to a distribution curve 12. [0005] A cell is read by comparing the cell's threshold voltage to a reference voltage V.sub.R that is above distribution curve 10 but below V.sub.0. If the cell's threshold voltage is below V.sub.R then the cell's contents are read as a one-bit. If the cell's threshold voltage is at or above V.sub.R then the cell's contents are read as a zero-bit. [0006] Over time, the threshold voltages of the cells that store zero-bits tend to drift downwards. Also shown in FIG. 1, as a dashed line, is a distribution curve 14 that represents the distribution of the threshold voltages of the cells that have been programmed to store zero-bits after the passage of a considerable amount of time. V.sub.1, V.sub.R and V.sub.0 are selected to be sufficiently far apart to preserve the reliability of the flash memory despite this drift of the threshold voltages. [0007] One goal of the designers of flash memories is to reduce the cost per bit of storing data. This is accomplished in two ways. The first way is to use fabrication processes that cram more cells into the same semiconductor area. The second way is to use multi-level cells (MLCs) that store more than one bit per cell. Both ways of reducing costs decrease the retention time of the data. For example, multiple bits are stored in a MLC by defining 2'' voltage bands, to store n bits, in place of the two voltage bands (above and below V.sub.R) of a SLC. Because the voltage bands of a MLC are necessarily narrower than the voltage bands of a comparable SLC, the threshold voltage of a MLC that has been programmed to store one or more zero-bits drifts down to the next band down sooner than the threshold voltage of a comparable SLC drifts below V.sub.R. Given that the logic values of cells are set by way of setting appropriate threshold voltages (the threshold voltage of a cell being a physical parameter of the cell), the value that a threshold voltage represents is implementation-dependent. In the standard SLC implementation, a threshold voltage lower than the reference voltage represents "one-logic" (i.e. a logic value of one) and a threshold voltage higher than the reference voltage represents "zero-logic" (i.e. a logic value of zero), but there is no reason why the opposite convention couldn't be implemented. In an MLC implementation, there is more than one reference voltage. [0008] In the present invention, the process of selectively writing (i.e. programming) data to flash memory involves changing logic values of selected memory cells, typically, in a SLC implementation, from one-logic to zero-logic. The process of selectively erasing data from flash memory involves changing values of selected memory cells, typically from zero-logic to one-logic. However, as explained above, this designation is arbitrary, and would be equally implementable in the opposite designation. [0009] Some flash memory devices are optimized to write data in pages, which are typically 512 or 2048 bytes in size. The most widely-known example of such flash memory devices uses NAND-type flash memory. The term "NAND-type" will be used throughout the present application to refer to flash memory technologies that are optimized to write data in full-page increments (as opposed to NOR-type flash memory in which data can be written at the word level). [0010] Storing data on a NAND-type flash memory comprises several steps. First, a Data Input command is issued, indicating the address of the page that should be written. Next, the data is transferred to the memory. Finally, a Page Program command is issued. (It should be noted that although specific command names vary among NAND-type flash memory manufacturers, the command structure for storing a full page is identical.) [0011] Existing NAND-type flash memories have one or more page buffers (i.e. memory cells with read/write capability), which receive the data before the data is programmed into the flash memory cells. Existing page-programming methods, for flash memory in which each flash memory cell contains one bit of information and erased flash memory cells have one-logic, implement the following steps: [0012] (1) Apply a programming voltage pulse only to flash memory cells that have zero-logic in the corresponding cells of the page buffer, where a programming voltage pulse is a single attempt to set a cell to the desired threshold voltage, typically many such pulses are required to achieve the required voltage level; [0013] (2) Read the data programmed into the memory; [0014] (3) Set the corresponding cells of the page buffer to one-logic for all flash memory cells that return zero-logic when read; [0015] (4) Repeat steps 1-3 until all cells in the page buffer contain one-logic or until the number of pulses exceeds the maximum number allowed; and [0016] (5) If the number of pulses exceeds the maximum number allowed, then return a failure status for the page-programming operation. [0017] Whenever the Page Program operation terminates with failure, the data that failed to be programmed has to be programmed into a different location in the flash memory. The page-programming method described above modifies the contents of the page buffer, making the method unusable for programming the data onto a different location. [0018] As a result, programming data onto a different location requires keeping a copy of that data in a backup RAM buffer. Allocating such a backup buffer may consume significant RAM capacity, and may raise costs significantly for low-end systems. In addition, if the flash memory device receives streaming data from a host system, the flash memory device needs to be able to write this data simultaneously both to the backup buffer and to the flash memory interface, otherwise performance will be deteriorated. This requirement, in turn, complicates the flash memory device's internal architecture. [0019] One example of a prior art device is the 1-GBit NAND TwinFlash.TM. (see datasheet HYF33DS1G[80/16]OCTI available from Infineon Technologies North America Corporation, 1730 North First Street, San Jose, Calif. 95112). While this prior art device features the capability to recover data from a flash buffer, the method of recovery is not elaborated in any detail in the cited datasheet. [0020] It would be desirable for low-end flash memory devices to be able to retrieve data that has been written to a page from the flash memory itself, in order to re-write the data to another page without the need to keep a backup copy of that data in the RAM buffer. SUMMARY OF THE INVENTION [0021] It is the purpose of the present invention to provide the ability to calculate the original value of every bit in a page buffer from the value of the same bit after a persistent data-writing failure and the value of the corresponding bit in the flash memory. By applying this calculation, the contents of the page buffer can be restored. [0022] For the purpose of clarity, several terms which follow are specifically defined for use within the context of this application. The terms "erasing" and "writing" are used in this application to refer to setting threshold voltages of a memory cell, where erasing sets the voltages to correspond to one-logic values, and writing sets the voltages to correspond to zero-logic values. The terms "writing" and "programming" are used interchangeably herein. The present invention applies to both single-level-cell (SLC) flash memories and multi-level-cell (MLC) flash memories. While the subsequent discussion focuses primarily on SLC cells, it will be clear to those skilled in the art how the present invention applies to MLC cells. [0023] The threshold voltage of a MLC represents a bit pattern. In a four-level cell, for example, a threshold voltage in the lowest threshold voltage range could represent the bit pattern 11, a threshold voltage in the second threshold voltage range could represent the bit pattern 10, a threshold voltage in the third threshold voltage range could represent the bit pattern 01 and a threshold voltage in the fourth (i.e. highest) threshold voltage range could represent the bit pattern 00. [0024] The term "programming cycle" is used in this application to refer to a single attempt, as described in the Field and Background section of the present application, to set a cell voltage to the necessary threshold voltage required for the programming operation. As mentioned above, in practice, multiple programming cycles are commonly necessary to achieve the desired voltage change. The term "persistent failure" is used in this application to refer to a failure response after a maximum number of unsuccessful programming cycles have been performed. [0025] The term "AND-logic operation" is used in this application to refer to operations where zero-logic AND zero-logic equal zero-logic, one-logic AND zero-logic equal zero-logic, zero-logic AND one-logic equal zero-logic, and one-logic AND one-logic equal one-logic. The term "OR-logic operation" is used in this application to refer to operations where zero-logic OR zero-logic equals zero-logic, one-logic OR zero-logic equals one-logic, zero-logic OR one-logic equals one-logic, and one-logic OR one-logic equals one-logic. [0026] Therefore, according to the present invention, there is provided for the first time a method for storing data, the method including the steps of: (a) setting bits of a data buffer in accordance with the data; (b) programming a plurality of memory cells in accordance with the data buffer; and (c) upon failure of the programming step, restoring the data buffer to be set in accordance with the data, wherein the restoring is based only on a present state of the data buffer and on a present state of the plurality of memory cells. [0027] Preferably, the memory cells are flash memory cells. Continue reading about Data restoration in case of page-programming failure... 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