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  Data processorUSPTO Application #: 20080046697Title: Data processor Abstract: The present invention prevents a data processor from undesirable operation stop due to an overflow of a plurality of register banks. A status register includes an overflow flag to indicate an overflow of the plurality of register banks. When an interrupt exception occurs in a state in which data has been saved to all banks of the register banks, and the accepted interrupt exception is permitted to use the register banks, a central processing unit saves data of a register set to a stack area and reflects an overflow state in the overflow flag. When the overflow flag indicates an overflow state, if data restoration from the register banks to the register set is directed, the central processing unit restores the data from the stack area to the register set. (end of abstract)
Agent: Miles & Stockbridge PC - Mclean, VA, US Inventors: Yasuo SUGURE, Tomomi ISHIKURA, Kazuya HIRAYANAGI, Takeshi KATAOKA, Seiji TAKEUCHI, Hiromichi YAMADA, Takanaga YAMAZAKI USPTO Applicaton #: 20080046697 - Class: 712218000 (USPTO) Related Patent Categories: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors), Dynamic Instruction Dependency Checking, Monitoring Or Conflict Resolution, Commitment Control Or Register Bypass The Patent Description & Claims data below is from USPTO Patent Application 20080046697. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] The present invention relates to a data processor including register banks, more particularly to register set saving and restoring involved in interrupt exception (refers to both interrupts and exceptions) handling and task switching, and a technique effectively applied to, e.g., single chip microcomputers. [0002] When interrupt exception handling or task switching under multitask environments is performed, a predetermined register set such as general purpose registers, a status register, and the like at that time is saved to enable restoration to a previous state. Although a stack area allocated to an external memory and the like can be used as a save destination, register banks can be used to rapidly save and restore the register set. Use of the register bank method shortens interrupt response time. [0003] Patent Publication 1 describes a single-chip microcomputer including general purpose registers of bank structure by use of an internal RAM (random access memory), provided with a dedicated bus for that purpose. Patent Publication 2 describes an information processing unit having a register bank configuration in which a dedicated bus is provided between a register file and an internal RAM. Patent Publication 3 describes an extended central processing unit having a register file configuration with a dedicated bus provided between the register file and an internal RAM. [Patent Publication 1] Japanese Unexamined Patent Publication No. Hei 5 (1993)-165641 [Patent Publication 2] Japanese Unexamined Patent Publication No. Hei 6 (1994)-309169 [Patent Publication 3] Japanese Unexamined Patent Publication No. Hei 5 (1993)-265753 SUMMARY OF THE INVENTION [0004] The inventor studied a register bank method to shortens interrupt response time. First, an overflow of register banks is taken into account. When an interrupt occurs, some interrupt service routines mask only a critical section having a high emergency level such as interrupt factor flag clear with the interrupt level, and after servicing the interrupt, accept re-input of interrupts of the same or lower levels. In such a case where interrupt service is performed by intentionally lowering interrupt levels, since more interrupts than the number of interrupt levels occur, register banks provided by the number of interrupt levels overflows. As a result, a CPU (central processing unit) taking no measures against overflow may fall into undesirable operation stop. [0005] Second, in the case where an OS (operating system) is used, task switching by interrupt is taken into account. Specifically, in task switching, after data of a register set before the task switching is saved to an OS internal table, data of the register set on tasks after the switching must be restored from the OS internal table to the register set. Unless such processing is performed, control cannot be returned to a previous task again. [0006] The present invention provides a technique for preventing a data processor from malfunctioning on saving and restoring register banks. [0007] An object of the present invention is to provide a data processor that is free from undesirable operation stop due to an overflow of register banks. [0008] Another object of the present invention is to provide a data processor that can smoothly and efficiently perform restoration from interrupts, whether task switching is involved or not, and is excellent in applicability to multitask processing. [0009] The foregoing and other objects, and novel features of the present invention will become apparent from this specification and the accompanying drawings. [0010] Representative examples of the invention disclosed in the present application will be briefly described below. [0011] [1] In a data processor that uses a status register and plural register banks to execute instructions, the status register includes an overflow flag to indicate an overflow of the plural register banks. [0012] As a further embodiment of the present invention, the data processor comprises: a status register; a central processing unit (CPU) including a predetermined register set; and a plurality of register banks corresponding to the predetermined register set, wherein the plurality of register banks are used to save storage information held by the predetermined register set when an interrupt occurs, and the status register includes an overflow flag to indicate an overflow of the plural register banks. [0013] By providing the overflow flag, when data is restored to the register set, an overflow of the register banks can be recognized. [0014] For example, when an interrupt exception occurs in a state in which data has been saved to all banks of the register banks, and the accepted interrupt exception is permitted to use the register banks, the central processing unit saves data of the register set to a stack area and reflects an overflow state in the overflow flag. When the overflow flag indicates an overflow state, if data restoration from the register banks to the register set is directed, the central processing unit restores the data from the stack area to the register set. [0015] It is to be noted that, in the interrupt exception handling, the status register including the overflow flag and the program counter are saved to a stack area, and an interrupt restore instruction (RTE instruction) restores the values of the program counter and the status register from the stack area. Specifically, even if interrupt service processing is multiplexed, any interrupt service routines can determine whether the register banks have overflowed due to an interrupt concerned by observing the overflow flag (overflow bit) in the status register. [0016] However, in cases where task switching by the OS is performed by interrupts, before execution of an instruction (RTE instruction) to restore from an interrupt service routine, a status register value corresponding to a switching destination task must be prepared in advance in a stack area where restore values are placed. This is operation indispensable to task switching processing in the OS and not extra processing added by the present invention. Continue reading... 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